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PRELIMINARY DRAFT CY7C68033/CY7C68034 EZ-USB NX2LP-FlexTM Flexible USB NAND Flash Controller
1.0 Silicon Features
* 12 fully-programmable GPIO pins * Integrated, industry-standard enhanced 8051 -- 48-MHz, 24-MHz, or 12-MHz CPU operation -- Four clocks per instruction cycle -- Three counter/timers -- Expanded interrupt system -- Two data pointers * 3.3V operation with 5V tolerant inputs * Vectored USB interrupts and GPIF/FIFO interrupts * Separate data buffers for the Set-up and Data portions of a CONTROL transfer * Four integrated FIFOs -- Integrated glue logic and FIFOs lower system cost -- Automatic conversion to and from 16-bit buses -- Master or slave operation -- Uses external clock or asynchronous strobes -- Easy interface to ASIC and DSP ICs * Available in space saving, 56-pin QFN package CY7C68034: * Ideal for battery powered applications -- Suspend current: 100 A (typ.) CY7C68033: * Ideal for non-battery powered applications -- Suspend current: 300 A (typ.) Both CY7C68033/CY7C68034: * USB 2.0-USB-IF high-speed certification pending * Single-chip, integrated USB 2.0 transceiver and smart SIE * Ultra low power - 43 mA typical current draw in any mode * Enhanced 8051 core -- Firmware runs from internal RAM, which is downloaded from NAND flash at startup -- No external EEPROM required * 15 KBytes of on-chip Code/Data RAM -- Default NAND firmware ~8 kB -- Default free space ~7 kB * Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints -- Buffering options: double, triple, and quad * Additional programmable (BULK/INTERRUPT) 64-byte endpoint * SmartMediaTM Standard Hardware ECC generation with 1bit correction and 2-bit detection * GPIF (General Programmable Interface) -- Allows direct connection to most parallel interfaces -- Programmable waveform descriptors and configuration registers to define waveforms -- Supports multiple Ready (RDY) inputs and Control (CTL) outputs
24 MHz Ext. Xtal
High-performance, enhanced 8051 core with low power options
NX2LP-Flex
x20 PLL /0.5 /1.0 /2.0 8051 Core 12/24/48 MHz, four clocks/cycle Address (16) / Data Bus (8)
Additional I/Os
Connected for full-speed USB
VCC 1.5k
NAND Boot Logic (ROM)
GPIF ECC
RDY (2) CTL (3)
General Programmable I/F to ASIC/DSP or bus standards such as 8-bit NAND, EPP, etc.
D+ D-
USB 2.0 XCVR
Integrated full- and high-speed XCVR
CY Smart USB 1.1/2.0 Engine
15 kB RAM
Up to 96 MB/s burst rate 4 kB FIFO
8/16
Enhanced USB core simplifies 8051 code
"Soft Configuration" enables easy firmware changes
FIFO and USB endpoint memory (master or slave modes)
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation Document #: 001-04247 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised July 15, 2005
PRELIMINARY DRAFT CY7C68033/CY7C68034
1.1 Default NAND Firmware Features
commands and data to the NX2LP-Flex and receives status and data from the NX2LP-Flex using standard USB protocol. The default firmware image supports industry leading 8-bit NAND Flash interfaces and both common NAND page sizes of 512 and 2k bytes. Up to eight chip enable pins allow the NX2LP-Flex to be connected to up to eight single- or four dualdie NAND Flash chips. Complete source code and documentation for the default firmware image are included in the NX2LP-Flex development kit to enable customization for meeting design requirements. Additionally, compile options for the default firmware allow for quick configuration of some features to decrease design effort and increase time-to-market advantages.
Because the NX2LP-FlexTM is intended for NAND Flashbased USB mass storage applications, a default firmware image is included in the development kit with the following features: * High (480-Mbps) or full (12-Mbps) speed USB support * Both common NAND page sizes supported -- 512 bytes for up to 1 Gb capacity -- 2K bytes for up to 8 Gb capacity * 12 configurable general-purpose I/O (GPIO) pins -- 2 dedicated chip enable (CE#) pins -- 6 configurable CE#/GPIO pins * Up to 8 NAND Flash single-device (single-die) chips are supported * Up to 4 NAND Flash dual-device (dual-die) chips are supported * Compile option allows unused CE# pins to be configured as GPIOs -- 4 dedicated GPIO pins * Industry standard ECC NAND Flash correction -- 1-bit per 256-bit correction -- 2-bit error detection * Industry standard (SmartMedia) page management for wear leveling algorithm, bad block handling, and Physical to Logical management. * 8-bit NAND Flash interface support * Support for 30-ns, 50-ns, and 100-ns NAND Flash timing * Complies with the USB Mass Storage Class Specification revision 1.0 The default firmware image implements a USB 2.0 NAND Flash controller. This controller adheres to the Mass Storage Class Bulk-Only Transport Specification. The USB port of the NX2LP-Flex is connected to a host computer directly or via the downstream port of a USB hub. Host software issues
2.0
Overview
Cypress Semiconductor Corporation's (Cypress's) EZ-USB NX2LP-Flex (CY7C68033/CY7C68034) is a firmware-based, programmable version of the EZ-USB NX2LPTM (CY7C68023/CY7C68024), which is a fixed-function, lowpower USB 2.0 NAND Flash controller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that enables feature-rich NAND Flash-based applications. The ingenious architecture of NX2LP-Flex results in USB data transfer rates of over 53 Mbytes per second, the maximumallowable USB 2.0 bandwidth, while still using a low-cost 8051 microcontroller in a small 56-pin QFN package. Because it incorporates the USB 2.0 transceiver, the NX2LP-Flex is more economical, providing a smaller footprint solution than external USB 2.0 SIE or transceiver implementations. With EZ-USB NX2LP-Flex, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol, freeing the embedded microcontroller for application-specific functions and decreasing development time while ensuring USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provide an easy and glueless interface to popular interfaces such as UTOPIA, EPP, I2C, PCMCIA, and most DSP processors.
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3.0 Applications 4.0
4.1
Functional Overview
USB Signaling Speed
The NX2LP-Flex allows designers to add extra functionality to basic NAND Flash mass storage designs, or to interface them with other peripheral devices. Applications may include: * NAND Flash-based GPS devices * NAND Flash-based DVB video capture devices * Wireless pointer/presenter tools with NAND Flash storage * NAND Flash-based MPEG/TV conversion devices * Legacy conversion devices with NAND Flash storage * NAND Flash-based cameras * NAND Flash mass storage device with biometric (e.g., fingerprint) security * Home PNA devices with NAND Flash storage * Wireless LAN with NAND Flash storage * NAND Flash-based MP3 players * LAN networking with NAND Flash storage
NX2LP-Flex operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000: * Full speed, with a signaling bit rate of 12 Mbps * High speed, with a signaling bit rate of 480 Mbps. NX2LP-Flex does not support the low-speed signaling mode of 1.5 Mbps.
4.2
8051 Microprocessor
The 8051 microprocessor embedded in the NX2LP-Flex has 256 bytes of register RAM, an expanded interrupt system and three timer/counters. 4.2.1 8051 Clock Frequency
NX2LP-Flex has an on-chip oscillator circuit that uses an external 24-MHz (100-ppm) crystal with the following characteristics: * Parallel resonant * Fundamental mode * 500-W drive level * 12-pF (5% tolerance) load capacitors.
NAND-Based DVB Unit
Buttons
I/O
LCD
D+/-
I/O
CTL
NX2LPFlex
CE[7:0] I/O
NAND Bank(s)
An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY, and internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically. C1 12 pf 24 MHz C2 12 pf
Audio / Video I/O
DVB Decoder
Figure 3-1. Example DVB Block Diagram 20 x PLL
NAND-Based GPS Unit
Buttons
I/O
12-pF capacitor values assumes a trace capacitance of 3 pF per side on a four-layer FR4 PCA
CTL
I/O
LCD
D+/-
I/O
Figure 4-1. Crystal Configuration
NAND Bank(s)
NX2LPFlex
CE[7:0] I/O
The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency--48, 24, or 12 MHz. 4.2.2 Special Function Registers
GPS
I/O
Figure 3-2. Example DVB Block Diagram The "Reference Designs" section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Please visit http://www.cypress.com for more information. Document #: 001-04247 Rev. *A
Certain 8051 SFR addresses are populated to provide fast access to critical NX2LP-Flex functions. These SFR additions are shown in Table 4-1. Bold type indicates non-standard, enhanced 8051 registers. The two SFR rows that end with "0" and "8" contain bit-addressable registers. The four I/O ports A-D use the SFR addresses used in the standard 8051 for ports 0-3, which are not implemented in NX2LP-Flex. Because of the faster and more efficient SFR addressing, the NX2LP-Flex I/O ports are not addressable in external RAM space (using the MOVX instruction). Page 3 of 40
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Table 4-1. Special Function Registers x 0 1 2 3 4 5 6 7 8 9 A B C D E F 8x IOA SP DPL0 DPH0 DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON 9x IOB EXIF MPAGE Ax IOC INT2CLR INT4CLR Bx IOD IOE OEA OEB OEC OED OEE IP EP01STAT GPIFTRIG GPIFSGLDATH GPIFSGLDATLX GPIFSGLDATLNOX Cx SCON1 SBUF1 Dx PSW Ex ACC Fx B
SCON0 SBUF0 AUTOPTRH1 AUTOPTRL1 RESERVED AUTOPTRH2 AUTOPTRL2 RESERVED
IE EP2468STAT EP24FIFOFLGS EP68FIFOFLGS
T2CON RCAP2L RCAP2H TL2 TH2
EICON
EIE
EIP
AUTOPTRSET-UP
4.3
Buses
4.4
Enumeration
The NX2LP-Flex features an 8- or 16-bit "FIFO" bidirectional data bus, multiplexed on I/O ports B and D. The default firmware image implements an 8-bit data bus in GPIF Master mode. It is recommended that additional interfaces added to the default firmware image use this 8-bit data bus.
During the start-up sequence, internal logic checks for the presence of NAND Flash with valid firmware. If valid firmware is found, the NX2LP-Flex loads it and operates according to the firmware. If no NAND Flash is detected, or if no valid firmware is found, the NX2LP-Flex uses the default values from internal ROM space for manufacturing mode operation. The two modes of operation are described in sections 4.4.1 and 4.4.2 below.
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4.5
Start-up
Default Silicon ID Values
Yes
NAND Flash Present?
No
To facilitate proper USB enumeration when no programmed NAND Flash is present, the NX2LP-Flex has default silicon ID values stored in ROM space. The default silicon ID values should only be used for development purposes. Cypress requires designers to use their own Vendor ID for final products. A Vendor ID is obtained through registration with the USB Implementor's Forum (USB-IF). Also, if the NX2LP-Flex is used as a mass storage class device, a unique USB serial number is required for each device in order to comply with the USB Mass Storage class specification. Cypress provides all the software tools and drivers necessary for properly programming and testing the NX2LP-Flex. Please refer to the documentation in the development kit for more information on these topics. Table 4-2. Default Silicon ID Values Vendor ID Product ID Device release Default VID/PID/DID 0x04B4 Cypress Semiconductor 0x8613 EZ-USB(R) Default 0xAnnn Depends on chip revision (nnn = chip revision, where first silicon = 001)
NAND Flash Programmed?
No
Yes
Load Firmware From NAND
Load Default Descriptors and Configuration Data
4.6
ReNumerationTM
Enumerate According To Firmware
Enumerate As Unprogrammed NX2LP-Flex
Cypress's ReNumerationTM feature is used in conjunction with the NX2LP-Flex manufacturing software tools to enable firsttime NAND programming. It is only available when used in conjunction with the NX2LP-Flex Manufacturing tools, and is not enabled during normal operation.
4.7
Bus-powered Applications
The NX2LP-Flex fully supports bus-powered designs by enumerating with less than 100 mA, as required by the USB 2.0 specification.
Normal Operation Mode Manufacturing Mode
4.8
4.8.1
Interrupt System
INT2 Interrupt Request and Enable Registers
Figure 4-2. NX2LP-Flex Enumeration Sequence 4.4.1 Normal Operation Mode
In Normal Operation Mode, the NX2LP-Flex behaves as a USB 2.0 Mass Storage Class NAND Flash controller. This includes all typical USB device states (powered, configured, etc.). The USB descriptors are returned according to the data stored in the configuration data memory area. Normal read and write access to the NAND Flash is available in this mode. 4.4.2 Manufacturing Mode
NX2LP-Flex implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See the EZ-USB Technical Reference Manual (TRM) for more details. 4.8.2 USB-Interrupt Autovectors
In Manufacturing Mode, the NX2LP-Flex enumerates using the default descriptors and configuration data that are stored in internal ROM space. This mode allows for first-time programming of the configuration data memory area, as well as board-level manufacturing tests.
The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that normally would be required to identify the individual USB interrupt source, the NX2LP-Flex provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the NX2LP-Flex pushes the program counter onto its stack then jumps to address 0x0500, where it expects to find a "jump" instruction to the USB Interrupt service routine. Developers familiar with Cypress's programmable USB devices should note that these interrupt vector values differ from those used in other EZ-USB microcontrollers. This is due to the additional NAND boot logic that is present in the NX2LPFlex ROM space. Also, these values are fixed and cannot be changed in the firmware.
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Table 4-3. INT2 USB Interrupts USB INTERRUPT TABLE FOR INT2 Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 INT2VEC Value 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0x528 0x52C 0x530 0x534 0x538 0x53C 0x540 0x544 0x548 0x54C 0x550 0x554 0x558 0x55C 0x560 0x564 0x568 0x56C 0x570 0x574 0x578 0x57C EP2ISOERR EP4ISOERR EP6ISOERR EP8ISOERR EP0PING EP1PING EP2PING EP4PING EP6PING EP8PING ERRLIMIT EP0-IN EP0-OUT EP1-IN EP1-OUT EP2 EP4 EP6 EP8 IBN SUDAV SOF SUTOK SUSPEND USB RESET HISPEED EP0ACK Source Set-up Data Available Start of Frame (or microframe) Set-up Token Received USB Suspend request Bus reset Entered high speed operation NX2LP ACK'd the CONTROL Handshake Reserved EP0-IN ready to be loaded with data EP0-OUT has USB data EP1-IN ready to be loaded with data EP1-OUT has USB data IN: buffer available. OUT: buffer has data IN: buffer available. OUT: buffer has data IN: buffer available. OUT: buffer has data IN: buffer available. OUT: buffer has data IN-Bulk-NAK (any IN endpoint) Reserved EP0 OUT was Pinged and it NAK'd EP1 OUT was Pinged and it NAK'd EP2 OUT was Pinged and it NAK'd EP4 OUT was Pinged and it NAK'd EP6 OUT was Pinged and it NAK'd EP8 OUT was Pinged and it NAK'd Bus errors exceeded the programmed limit Reserved Reserved Reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error 4.8.3 FIFO/GPIF Interrupt (INT4) Notes
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the NX2LP-Flex substitutes its INT2VEC byte. Therefore, if the high byte ("page") of a jump-table address is preloaded at location 0x544, the automatically-inserted INT2VEC byte at 0x545 will direct the jump to the correct address out of the 27 addresses within the page.
Just as the USB Interrupt is shared among 27 individual USBinterrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 4-4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.
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Table 4-4. Individual FIFO/GPIF Interrupt Sources Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 INT4VEC Value 0x580 0x584 0x588 0x58C 0x590 0x594 0x598 0x59C 0x5A0 0x5A4 0x5A8 0x5AC 0x5B0 0x5B4 Source EP2PF EP4PF EP6PF EP8PF EP2EF EP4EF EP6EF EP8EF EP2FF EP4FF EP6FF EP8FF GPIFDONE GPIFWF Notes Endpoint 2 Programmable Flag Endpoint 4 Programmable Flag Endpoint 6 Programmable Flag Endpoint 8 Programmable Flag Endpoint 2 Empty Flag Endpoint 4 Empty Flag Endpoint 6 Empty Flag Endpoint 8 Empty Flag Endpoint 2 Full Flag Endpoint 4 Full Flag Endpoint 6 Full Flag Endpoint 8 Full Flag GPIF Operation Complete GPIF Waveform reset period must allow for the stabilization of the crystal and the PLL. This reset period should be approximately 5 ms after VCC has reached 3.0V. If the crystal input pin is driven by a clock signal, the internal PLL stabilizes in 200 s after VCC has reached 3.0V[1]. Figure 4-3 shows a power-on reset condition and a reset applied during operation. A power-on reset is defined as the time reset is asserted while power is being applied to the circuit. A powered reset is defined to be when the NX2LP-Flex has previously been powered on and operating and the RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation and can be found on the Cypress web site. For more information on reset implementation for the EZ-USB family of products visit the http://www.cypress.com website.
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP register), the NX2LP-Flex substitutes its INT4VEC byte. Therefore, if the high byte ("page") of a jump-table address is preloaded at location 0x554, the automatically-inserted INT4VEC byte at 0x555 will direct the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the NX2LP-Flex pushes the program counter onto its stack then jumps to address 0x553, where it expects to find a "jump" instruction to the ISR Interrupt service routine.
4.9
4.9.1
Reset and Wakeup
Reset Pin
The input pin RESET#, will reset the NX2LP-Flex when asserted. This pin has hysteresis and is active LOW. When a crystal is used as the clock source for the NX2LP-Flex, the
Note: 1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 s.
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RESET#
RESET#
VIL 3.3V 3.0V VCC 0V TRESET
Power on Reset
VIL 3.3V VCC 0V TRESET
Powered Reset
Figure 4-3. Reset Timing Plots Table 4-5. Reset Timing Values Condition Power-on Reset with crystal Power-on Reset with external clock source Powered Reset 4.9.2 Wakeup Pins TRESET 5 ms 200 s + Clock stability time 200 s 4.10.2 Internal Code Memory
This mode implements the internal block of RAM (starting at 0x0500) as combined code and data memory, as shown in Figure 4-4, below. Only the internal and scratch pad RAM spaces have the following access: * USB download (only supported by the Cypress Manufacturing Tool) * Set-up data pointer * NAND boot access.
FFFF 7.5 kBytes USB registers and 4 kBytes FIFO buffers (RD#, WR#) 512 Bytes RAM Data (RD#, WR#)*
The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic, the oscillator restarts, after the PLL stabilizes, and then the 8051 receives a wakeup interrupt. This applies whether or not NX2LP-Flex is connected to the USB. The NX2LP-Flex exits the power-down (USB suspend) state using one of the following methods: * USB bus activity (if D+/D- lines are left floating, noise on these lines may indicate activity to the NX2LP-Flex and initiate a wakeup). * External logic asserts the WAKEUP pin * External logic asserts the PA3/WU2 pin. The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network to be used as a periodic wakeup source. Note that WAKEUP is, by default, active LOW.
E200 E1FF E000
3FFF
15 kBytes RAM Code and Data (PSEN#, RD#, WR#)* 0500 0000 1 kbyte ROM
4.10
4.10.1
Program/Data RAM
Internal ROM/RAM Size
*SUDPTR, USB download, NAND boot access
The NX2LP-Flex has 1 kBytes ROM and 15 kBytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to allow the 8051 to access it as both program and data memory. No USB control registers appear in this space.
Figure 4-4. Internal Code Memory
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4.11 Register Addresses
FFFF 4 KBytes EP2-EP8 buffers (8 x 512)
4.12.2 * EP0
Organization
-- Bidirectional endpoint zero, 64-byte buffer * EP1IN, EP1OUT -- 64-byte buffers, bulk or interrupt * EP2,4,6,8
F000 EFFF 2 KBytes RESERVED E800 E7FF E7C0 E7BF E780 E77F E740 64 Bytes EP1IN 64 Bytes EP1OUT 64 Bytes EP0 IN/OUT 64 Bytes RESERVED 8051 Addressable Registers (512) Reserved (128) 128 bytes GPIF Waveforms Reserved (512)
-- Eight 512-byte buffers, bulk, interrupt, or isochronous. -- EP4 and EP8 can be double buffered, while EP2 and 6 can be either double, triple, or quad buffered. For high-speed endpoint configuration options, see Figure 4-6. 4.12.3 Set-up Data Buffer
E73F
E700 E6FF E500 E4FF E480 E47F E400 E3FF E200 E1FF
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Set-up data from a CONTROL transfer. 4.12.4 Endpoint Configurations (High-speed Mode)
512 bytes 8051 xdata RAM E000
Figure 4-5. Internal Register Addresses
Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. The endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns. When operating in full-speed BULK mode, only the first 64 bytes of each buffer are used. For example, in high-speed the max packet size is 512 bytes, but in full-speed it is 64 bytes. Even though a buffer is configured to be a 512 byte buffer, in full-speed only the first 64 bytes are used. The unused endpoint buffer space is not available for other operations. An example endpoint configuration would be: EP2-1024 double buffered; (column 8 in Figure 4-6). EP6-512 quad buffered
4.12
4.12.1
Endpoint RAM
Size (Endpoints 0 and 1)
* 3 x 64 bytes
* 8 x 512 bytes (Endpoints 2, 4, 6, 8)
EP0 IN&OUT EP1 IN EP1 OUT 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64
EP2
512 512
EP2
512 512
EP2
512 512
EP2
512 512
EP2
512 512
EP2
512 512
EP2
1024
EP2
1024
EP2
1024
EP2
512
EP2 EP2
1024 1024
512
512
EP4
512 512
EP4
512 512
EP4
512 512 512 512 512 512 512 512 1024 1024 1024
EP6
512
1024
1024
EP6
512 512
EP6
512 512
EP6
1024
EP6
512 512
EP6
512 512
EP6
1024
EP6
512 512
EP6
512 512
EP6
1024
512 512
1024 1024
1024
EP8
512 512 512 512 1024
EP8
512 512 512 512 1024
EP8
512 512 512 512 1024
EP8
512 512
EP8
512 512 1024
1
2
3
4
5
6
7
8
9
10
11
12
Figure 4-6. Endpoint Configuration Document #: 001-04247 Rev. *A Page 9 of 40
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4.12.5 Default Full-Speed Alternate Settings
Table 4-6. Default Full-Speed Alternate Settings[2, 3] Alternate Setting ep0 ep1out ep1in ep2 ep4 ep6 ep8 4.12.6 0 64 0 0 0 0 0 0 64 64 bulk 64 bulk 64 bulk out (2x) 64 bulk out (2x) 64 bulk in (2x) 64 bulk in (2x) 1 64 64 int 64 int 64 int out (2x) 64 bulk out (2x) 64 int in (2x) 64 bulk in (2x) 2 64 64 int 64 int 64 iso out (2x) 64 bulk out (2x) 64 iso in (2x) 64 bulk in (2x) 3
Default High-Speed Alternate Settings
Table 4-7. Default High-Speed Alternate Settings[2, 3] Alternate Setting ep0 ep1out ep1in ep2 ep4 ep6 ep8 64 0 0 0 0 0 0 0 64 512 bulk[4] 512 bulk[4] 512 bulk out (2x) 512 bulk out (2x) 512 bulk in (2x) 512 bulk in (2x) 1 64 64 int 64 int 512 int out (2x) 512 bulk out (2x) 512 int in (2x) 512 bulk in (2x) 2 64 64 int 64 int 512 iso out (2x) 512 bulk out (2x) 512 iso in (2x) 512 bulk in (2x) 3
4.13
4.13.1
External FIFO Interface
Architecture
The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface. In Master (M) mode, the GPIF internally controls FIFOADR[1:0] to select a FIFO. The two RDY pins can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16bit interface). In Slave (S) mode, the NX2LP-Flex accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. When using an external IFCLK, the external clock must be present before switching from the internal clock source with the IFCLKSRC bit. Each endpoint can individually be selected for byte or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#. 4.13.3 GPIF and FIFO Clock Rates
The NX2LP-Flex slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags). In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic. The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally controlled transfers. 4.13.2 Master/Slave Control Signals
The NX2LP-Flex endpoint FIFOS are implemented as eight physically distinct 256x16 RAM blocks. The 8051/SIE can switch any of the RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instantaneously, giving essentially zero transfer time between "USB FIFOS" and "Slave FIFOS." Since they are physically the same memory, no bytes are actually transferred between buffers. At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available to the 8051 and/or the I/O control unit. The RAM blocks operate as single-port in the USB domain, and dualport in the 8051-I/O domain. The blocks can be configured as single, double, triple, or quad buffered as previously shown.
An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alter-
Notes: 2. "0" means "not implemented." 3. "2x" means "double buffered." 4. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
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natively, an externally supplied clock of 5 MHz-48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as a clock output signal when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register turns this clock output off, if desired. Another bit within the IFCONFIG register will invert the IFCLK signal, whether internally or externally sourced. The default NAND firmware image implements a 48-MHz internally supplied interface clock and disables the IFCLK output. The NAND boot logic uses the same configuration to implement 100-ns timing on the NAND bus to support proper detection of all NAND Flash types. The GPIF automatically throttles data flow to prevent under- or over-flow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction.
4.15
ECC Generation[5]
The NX2LP-Flex can calculate ECCs (Error-Correcting Codes) on data that passes across its GPIF or Slave FIFO interfaces. There are two ECC configurations: * Two ECCs, each calculated over 256 bytes (SmartMedia Standard) * One ECC calculated over 512 bytes. The two ECC configurations described below are selected by the ECCM bit. The ECC can correct any one-bit error or detect any two-bit error. 4.15.1 ECCM = 0
4.14
GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the NX2LPFlex to perform local bus mastering, and can implement a wide variety of protocols such as 8-bit NAND interface, printer parallel port, and Utopia. The default NAND firmware and boot logic utilizes GPIF functionality to interface with NAND Flash. The GPIF on the NX2LP-Flex features three programmable control outputs (CTL) and two general-purpose ready inputs (RDY). The GPIF data bus width can be 8 or 16 bits. Because the default NAND firmware image implements an 8-bit data bus and up to 8 chip enable pins on the GPIF ports, it is recommended that designs based upon the default firmware image use an 8-bit data bus as well. Each GPIF vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that will be executed to perform the desired data move between the NX2LP-Flex and the external device. 4.14.1 Three Control OUT Signals
Two 3-byte ECCs, each calculated over a 256-byte block of data. This configuration conforms to the SmartMedia Standard and is used by both the NAND boot logic and default NAND firmware image. When any value is written to ECCRESET and data is then passed across the GPIF or Slave FIFO interface, the ECC for the first 256 bytes of data will be calculated and stored in ECC1. The ECC for the next 256 bytes of data will be stored in ECC2. After the second ECC is calculated, the values in the ECCx registers will not change until ECCRESET is written again, even if more data is subsequently passed across the interface. 4.15.2 ECCM = 1
One 3-byte ECC calculated over a 512-byte block of data. When any value is written to ECCRESET and data is then passed across the GPIF or Slave FIFO interface, the ECC for the first 512 bytes of data will be calculated and stored in ECC1; ECC2 is unused. After the ECC is calculated, the value in ECC1 will not change until ECCRESET is written again, even if more data is subsequently passed across the interface
The NX2LP-Flex exposes three control signals, CTL[2:0]. CTLx waveform edges can be programmed to make transitions as fast as once per clock (20.8 ns using a 48-MHz clock). 4.14.2 Two Ready IN Signals
4.16
Autopointer Access
The 8051 programs the GPIF unit to test the RDY pins for GPIF branching. The 56-pin package brings out two signals, RDY[1:0]. 4.14.3 Long Transfer Mode
NX2LP-Flex provides two identical autopointers. They are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment after every memory access. Also, the autopointers can point to any NX2LP-Flex register or endpoint buffer space.
In GPIF Master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 232 transactions.
Notes: 5. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
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5.0 Pin Assignments
utilizes GPIF Master mode. The signals on the left edge of the "Port" column are common to all modes of the NX2LP-Flex. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power-on default configuration. Figure 5-2 details the pinout of the 56-pin package and lists pin names for all modes of operation. Pin names with an asterisk (*) feature programmable polarity.
Figure 5-1 and Figure 5-2 identify all signals for the 56-pin NX2LP-Flex package. Three modes of operation are available for the NX2LP-Flex: Port mode, GPIF Master mode, and Slave FIFO mode. These modes define the signals on the right edge of each column in Figure 5-1. The right-most column details the signal functionality from the default NAND firmware image, which actually
Port
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
GPIF Master
XTALIN XTALOUT RESET# WAKEUP#
DPLUS DMINUS
PA7 PA6 PA5 PA4 WU2/PA3 PA2 INT1#/PA1 INTO#/PA0 IFCLK CLKOUT
FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] RDY0 RDY1 CTL0 CTL1 CTL2 PA7 PA6 PA5 PA4 PA3/WU2 PA2 PA1/INT1# PA0/INT0# IFCLK CLKOUT
FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] SLRD SLWR FLAGA FLAGB FLAGC FLAGD/SLCS#/PA7 PKTEND FIFOADR1 FIFOADR0 PA3/WU2 SLOE PA1/INT1# PA0/INT0# IFCLK CLKOUT
Slave FIFO
CE7#/GPIO7 CE6#/GPIO6 CE5#/GPIO5 CE4#/GPIO4 CE3#/GPIO3 CE2#/GPIO2 CE1# CE0# DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 R_B1# R_B2# WE# RE0# RE1# GPIO1 GPIO0 WP_SW# WP_NF# LED2# LED1# ALE CLE GPIO8 GPIO9
Default NAND Firmware Use
Figure 5-1. Port and Signal Mapping
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*WAKEUP
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
CLKOUT
GND
56
GND
VCC
55
VCC
54
53
52
51
50
49
48
47
46
45
44
43
RDY0/*SLRD RDY1/*SLWR AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS
1 2 3 4 5 6 7 8 9
42 41 40 39 38
RESET# GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2 PA2/*SLOE PA1/INT1# PA0/INT0# VCC CTL2/*FLAGC CTL1/*FLAGB CTL0/*FLAGA
CY7C68033/CY7C68034 56-pin QFN
37 36 35 34 33 32 31 30 29
AGND 10 VCC 11 GND 12 *IFCLK 13 RESERVED# 14
15 Document #: 001-04247 Rev. *A 16 17 18 19 20 21 22 23 24 25 26 27 28
Figure 5-2. CY7C68033/CY7C68034 56-pin QFN Pin Assignment
RESERVED
RESERVED
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
GND
VCC
GND
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5.1 Pin Descriptions
NAND Default Pin Firmware Default Name Usage Pin Type State DMINUS DPLUS RESET# XTALIN N/A N/A N/A N/A I/O/Z I/O/Z Input Input Z Z N/A N/A
Table 5-1. NX2LP-Flex Pin Descriptions [6] 56 QFN Pin Number 9 8 42 5
Description USB D- Signal. Connect to the USB D- signal. USB D+ Signal. Connect to the USB D+ signal. Active LOW Reset. Resets the entire chip. See section 4.9 "Reset and Wakeup" on page 7 for more details. Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND. It is also correct to drive XTALIN with an external 24-MHz square wave derived from another clock source. When driving from an external source, the driving signal should be a 3.3V square wave. Crystal Output. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open.
4
XTALOUT
N/A
Output
N/A
54
CLKOUT
GPIO9
O/Z
12 MHz CLKOUT: 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input clock. The 8051 defaults to 12-MHz operation. The 8051 may threestate this output by setting CPUCS[1] = 1. N/A Multiplexed pin whose function is selected by IFCONFIG[1:0]. RDY0 is a GPIF input signal. SLRD is the input-only read strobe with programmable polarity (FIFOPINPOLAR[3]) for the slave FIFOs connected to FD[7:0] or FD[15:0]. R_B1# is a NAND Ready/Busy input signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. RDY1 is a GPIF input signal. SLWR is the input-only write strobe with programmable polarity (FIFOPINPOLAR[2]) for the slave FIFOs connected to FD[7:0] or FD[15:0]. R_B2# is a NAND Ready/Busy input signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. WE# is the NAND write enable output signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL1 is a GPIF control output. FLAGB is a programmable slave-FIFO output status flag signal. Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins. RE0# is a NAND read enable output signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL2 is a GPIF control output. FLAGC is a programmable slave-FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins. RE1# is a NAND read enable output signal. Interface Clock, used for synchronously clocking data into or out of the slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF. When internal clocking is used (IFCONFIG[7] = 1) the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG[5] and IFCONFIG[6]. IFCLK may be inverted, whether internally or externally sourced, by setting the bit IFCONFIG[4] =1.
1
RDY0 or SLRD
R_B1#
Input
2
RDY1 or SLWR
R_B2#
Input
N/A
29
CTL0 or FLAGA
WE#
O/Z
H
30
CTL1 or FLAGB
RE0#
O/Z
H
31
CTL2 or FLAGC
RE1#
O/Z
H
13
IFCLK
GPIO8
I/O/Z
I
Note: 6. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up and in standby. Note also that no pins should be driven while the device is powered down.
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Table 5-1. NX2LP-Flex Pin Descriptions (continued)[6] 56 QFN Pin Number 14 15 16 44 NAND Default Pin Firmware Default Name Usage Pin Type State Reserved# Reserved WAKEUP N/A N/A Unused Input Input Input N/A N/A N/A Reserved. Connect to VCC. USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Holding WAKEUP asserted inhibits the EZ-USB(R) chip from suspending. This pin has programmable polarity, controlled by WAKEUP[4]. Multiplexed pin whose function is selected by PORTACFG[0] PA0 is a bidirectional IO port pin. INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either edge triggered (IT0 = 1) or level triggered (IT0 = 0). CLE is the NAND Command Latch Enable signal. Multiplexed pin whose function is selected by PORTACFG[1] PA1 is a bidirectional IO port pin. INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either edge triggered (IT1 = 1) or level triggered (IT1 = 0). ALE is the NAND Address Latch Enable signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA2 is a bidirectional IO port pin. SLOE is an input-only output enable with programmable polarity (FIFOPINPOLAR[4]) for the slave FIFOs connected to FD[7:0] or FD[15:0]. LED1# is the data activity indicator LED sink pin. Multiplexed pin whose function is selected by WAKEUP[7] and OEA[3] PA3 is a bidirectional I/O port pin. WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit (WAKEUP[1]) and polarity set by WU2POL (WAKEUP[4]). If the 8051 is in suspend and WU2EN = 1, a transition on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Asserting this pin inhibits the chip from suspending, if WU2EN = 1. LED2# is the chip activity indicator LED sink pin. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA4 is a bidirectional I/O port pin. FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. WP_NF# is the NAND write-protect control output signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. WP_SW# is the NAND write-protect switch input signal. Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits. PA6 is a bidirectional I/O port pin. PKTEND is an input used to commit the FIFO packet data to the endpoint and whose polarity is programmable via FIFOPINPOLAR[5]. GPIO1 is a general purpose I/O signal. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and PORTACFG[7] bits. PA7 is a bidirectional I/O port pin. FLAGD is a programmable slave-FIFO output status flag signal. SLCS# gates all other slave FIFO enable/strobes GPIO0 is a general purpose I/O signal. Page 15 of 40
Description Reserved. Connect to ground.
Port A 33 PA0 or INT0# CLE I/O/Z I (PA0)
34
PA1 or INT1#
ALE
I/O/Z
I (PA1)
35
PA2 or SLOE or
LED1#
I/O/Z
I (PA2)
36
PA3 or WU2
LED2#
I/O/Z
I (PA3)
37
PA4 or FIFOADR0
WP_NF#
I/O/Z
I (PA4)
38
PA5 or FIFOADR1
WP_SW#
I/O/Z
I (PA5)
39
PA6 or PKTEND
GPIO0 (Input)
I/O/Z
I (PA6)
40
PA7 or FLAGD or SLCS#
GPIO1 (Input)
I/O/Z
I (PA7)
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Table 5-1. NX2LP-Flex Pin Descriptions (continued)[6] 56 QFN Pin Number Port B 18 PB0 or FD[0] DD0 I/O/Z I (PB0) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB0 is a bidirectional I/O port pin. FD[0] is the bidirectional FIFO/GPIF data bus. DD0 is a bidirectional NAND data bus signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB1 is a bidirectional I/O port pin. FD[1] is the bidirectional FIFO/GPIF data bus. DD1 is a bidirectional NAND data bus signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB2 is a bidirectional I/O port pin. FD[2] is the bidirectional FIFO/GPIF data bus. DD2 is a bidirectional NAND data bus signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus. DD3 is a bidirectional NAND data bus signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB4 is a bidirectional I/O port pin. FD[4] is the bidirectional FIFO/GPIF data bus. DD4 is a bidirectional NAND data bus signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB5 is a bidirectional I/O port pin. FD[5] is the bidirectional FIFO/GPIF data bus. DD5 is a bidirectional NAND data bus signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB6 is a bidirectional I/O port pin. FD[6] is the bidirectional FIFO/GPIF data bus. DD6 is a bidirectional NAND data bus signal. Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB7 is a bidirectional I/O port pin. FD[7] is the bidirectional FIFO/GPIF data bus. DD7 is a bidirectional NAND data bus signal. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. CE0# is a NAND chip enable output signal. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. CE1# is a NAND chip enable output signal. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[10] is the bidirectional FIFO/GPIF data bus. CE2# is a NAND chip enable output signal. GPIO2 is a general purpose I/O signal. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[11] is the bidirectional FIFO/GPIF data bus. CE3# is a NAND chip enable output signal. GPIO3 is a general purpose I/O signal. NAND Default Pin Firmware Default Name Usage Pin Type State
Description
19
PB1 or FD[1]
DD1
I/O/Z
I (PB1)
20
PB2 or FD[2]
DD2
I/O/Z
I (PB2)
21
PB3 or FD[3]
DD3
I/O/Z
I (PB3)
22
PB4 or FD[4]
DD4
I/O/Z
I (PB4)
23
PB5 or FD[5]
DD5
I/O/Z
I (PB5)
24
PB6 or FD[6]
DD6
I/O/Z
I (PB6)
25
PB7 or FD[7]
DD7
I/O/Z
I (PB7)
PORT D 45 PD0 or FD[8] CE0# I/O/Z I (PD0)
46
PD1 or FD[9]
CE1#
I/O/Z
I (PD1)
47
PD2 or FD[10]
CE2# or GPIO2
I/O/Z
I (PD2)
48
PD3 or FD[11]
CE3# or GPIO3
I/O/Z
I (PD3)
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Table 5-1. NX2LP-Flex Pin Descriptions (continued)[6] 56 QFN Pin Number 49 NAND Default Pin Firmware Default Name Usage Pin Type State PD4 or FD[12] CE4# or GPIO4 I/O/Z I (PD4)
Description Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[12] is the bidirectional FIFO/GPIF data bus. CE4# is a NAND chip enable output signal. GPIO4 is a general purpose I/O signal. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[13] is the bidirectional FIFO/GPIF data bus. CE5# is a NAND chip enable output signal. GPIO5 is a general purpose I/O signal. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[14] is the bidirectional FIFO/GPIF data bus. CE6# is a NAND chip enable output signal. GPIO6 is a general purpose I/O signal. Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[15] is the bidirectional FIFO/GPIF data bus. CE7# is a NAND chip enable output signal. GPIO7 is a general purpose I/O signal. Analog VCC. Connect this pin to 3.3V power source. This signal provides power to the analog section of the chip. Analog Ground. Connect to ground with as short a path as possible. VCC. Connect to 3.3V power source.
50
PD5 or FD[13]
CE5# or GPIO5
I/O/Z
I (PD5)
51
PD6 or FD[14]
CE6# or GPIO6
I/O/Z
I (PD6)
52
PD7 or FD[15]
CE7# or GPIO7
I/O/Z
I (PD7)
Power and Ground 3 7 6 10 11 17 27 32 43 55 12 26 28 41 53 56 AVCC AGND VCC N/A N/A N/A Power Ground Power N/A N/A N/A
GND
N/A
Ground
N/A
Ground.
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6.0 Register Summary
NX2LP-Flex register bit definitions are described in the EZ-USB TRM in greater detail. Some registers that are listed here and in the TRM do not apply to the NX2LP-Flex. They are kept here for consistency reasons only. Registers that do not apply to the NX2LP-Flex should be left at their default power-up values. Table 6-1. NX2LP-Flex Register Summary
Hex E400 E480 E50D E600 E601 E602 E603 E604 E605 E606 E607 E608 E609 E60A Size Name Description b7 GPIF Waveform Memories 128 WAVEDATA GPIF Waveform D7 Descriptor 0, 1, 2, 3 data 128 reserved GENERAL CONFIGURATION GPCR2 General Purpose Configu- reserved ration Register 2 1 CPUCS CPU Control & Status 0 1 IFCONFIG Interface Configuration IFCLKSRC (Ports, GPIF, slave FIFOs) [7] 1 PINFLAGSAB Slave FIFO FLAGA and FLAGB3 FLAGB Pin Configuration 1 PINFLAGSCD[7] Slave FIFO FLAGC and FLAGD3 FLAGD Pin Configuration [7] 1 FIFORESET Restore FIFOS to default NAKALL state 1 BREAKPT Breakpoint Control 0 1 BPADDRH Breakpoint Address H A15 1 BPADDRL Breakpoint Address L A7 1 UART230 230 Kbaud internally 0 generated ref. clock 1 FIFOPINPOLAR[7] Slave FIFO Interface pins 0 polarity 1 REVID Chip Revision rv7 REVCTL[7] Chip Revision Control UDMA GPIFHOLDAMOUNT MSTB Hold Time (for UDMA) reserved ENDPOINT CONFIGURATION EP1OUTCFG Endpoint 1-OUT Configuration EP1INCFG Endpoint 1-IN Configuration EP2CFG Endpoint 2 Configuration EP4CFG Endpoint 4 Configuration EP6CFG Endpoint 6 Configuration EP8CFG Endpoint 8 Configuration reserved EP2FIFOCFG[7] Endpoint 2 / slave FIFO configuration [7] EP4FIFOCFG Endpoint 4 / slave FIFO configuration [7] EP6FIFOCFG Endpoint 6 / slave FIFO configuration [7] EP8FIFOCFG Endpoint 8 / slave FIFO configuration reserved EP2AUTOINLENH[7 Endpoint 2 AUTOIN Packet Length H EP2AUTOINLENL[7] Endpoint 2 AUTOIN Packet Length L EP4AUTOINLENH[7] Endpoint 4 AUTOIN Packet Length H EP4AUTOINLENL[7] Endpoint 4 AUTOIN Packet Length L EP6AUTOINLENH[7] Endpoint 6 AUTOIN Packet Length H EP6AUTOINLENL[7] Endpoint 6 AUTOIN Packet Length L EP8AUTOINLENH[7] EP8AUTOINLENL ECCCFG ECCRESET ECC1B0 ECC1B1
[7]
b6 D6
b5 D5
b4 D4
b3 D3
b2 D2
b1 D1
b0 D0
Default xxxxxxxx
Access RW
reserved 0 3048MHZ FLAGB2 FLAGD2 0 0 A14 A6 0 0 rv6 0 0
FULL_SPEE reserved D_ONLY PORTCSTB CLKSPD1 CLKSPD0 IFCLKOE IFCLKPOL ASYNC FLAGB1 FLAGD1 0 0 A13 A5 0 PKTEND rv5 0 0 FLAGB0 FLAGD0 0 0 A12 A4 0 SLOE rv4 0 0 FLAGA3 FLAGC3 EP3 BREAK A11 A3 0 SLRD rv3 0 0
reserved
reserved CLKINV GSTATE FLAGA2 FLAGC2 EP2 BPPULSE A10 A2 0 SLWR rv2 0 0
reserved CLKOE IFCFG1 FLAGA1 FLAGC1 EP1 BPEN A9 A1 230UART1 EF rv1 dyn_out
reserved 8051RES IFCFG0 FLAGA0 FLAGC0 EP0 0 A8 A0 230UART0 FF rv0 enh_pkt
00000000 R 00000010 rrbbbbbr 10000000 RW 00000000 RW 00000000 RW xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 00000000 W rrrrbbbr RW RW rrrrrrbb
00000000 rrbbbbbb RevA R 00000001 00000000 rrrrrrbb
E60B 1 E60C 1 3 E610 1 E611 1 E612 E613 E614 E615 1 1 1 1 2 E618 1 E619 1 E61A 1 E61B 1 E61C 4 E620 1 E621 1 E622 1 E623 1 E624 1 E625 1 E626 1 E627 1 E628 E629 E62A E62B 1 1 1 1
0 0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
VALID VALID VALID VALID VALID VALID 0 0 0 0
0 0 DIR DIR DIR DIR INFM1 INFM1 INFM1 INFM1
TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 OEP1 OEP1 OEP1 OEP1
TYPE0 TYPE0 TYPE0 TYPE0 TYPE0 TYPE0 AUTOOUT AUTOOUT AUTOOUT AUTOOUT
0 0 SIZE 0 SIZE 0 AUTOIN AUTOIN AUTOIN AUTOIN
0 0 0 0 0 0
0 0 BUF1 0 BUF1 0
0 0 BUF0 0 BUF0 0
10100000 brbbrrrr 10100000 brbbrrrr 10100010 10100000 11100010 11100000 bbbbbrbb bbbbrrrr bbbbbrbb bbbbrrrr
ZEROLENIN 0 ZEROLENIN 0 ZEROLENIN 0 ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb WORDWIDE 00000101 rbbbbbrb WORDWIDE 00000101 rbbbbbrb WORDWIDE 00000101 rbbbbbrb
0 PL7 0 PL7 0 PL7 0 PL7 0 x LINE15 LINE7
0 PL6 0 PL6 0 PL6 0 PL6 0 x LINE14 LINE6
0 PL5 0 PL5 0 PL5 0 PL5 0 x LINE13 LINE5
0 PL4 0 PL4 0 PL4 0 PL4 0 x LINE12 LINE4
0 PL3 0 PL3 0 PL3 0 PL3 0 x LINE11 LINE3
PL10 PL2 0 PL2 PL10 PL2 0 PL2 0 x LINE10 LINE2
PL9 PL1 PL9 PL1 PL9 PL1 PL9 PL1 0 x LINE9 LINE1
PL8 PL0 PL8 PL0 PL8 PL0 PL8 PL0 ECCM x LINE8 LINE0
00000010 rrrrrbbb 00000000 RW 00000010 rrrrrrbb 00000000 RW 00000010 rrrrrbbb 00000000 RW 00000010 rrrrrrbb 00000000 RW 00000000 00000000 00000000 00000000 rrrrrrrb W R R
Endpoint 8 AUTOIN Packet Length H Endpoint 8 AUTOIN Packet Length L ECC Configuration ECC Reset ECC1 Byte 0 Address ECC1 Byte 1 Address
Note: 7. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for "Synchronization Delay."
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PRELIMINARY DRAFT CY7C68033/CY7C68034
Table 6-1. NX2LP-Flex Register Summary (continued)
Hex E62C E62D E62E E62F E630 H.S. E630 F.S. E631 H.S. E631 F.S E632 H.S. E632 F.S E633 H.S. E633 F.S E634 H.S. E634 F.S E635 H.S. E635 F.S E636 H.S. E636 F.S E637 H.S. E637 F.S Size 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Name ECC1B2 ECC2B0 ECC2B1 ECC2B2 EP2FIFOPFH[7] EP2FIFOPFH[7] EP2FIFOPFL
[7]
EP2FIFOPFL[7] EP4FIFOPFH EP4FIFOPFH EP4FIFOPFL
[7] [7]
[7]
EP4FIFOPFL[7] EP6FIFOPFH
[7]
EP6FIFOPFH[7] EP6FIFOPFL[7] EP6FIFOPFL[7] EP8FIFOPFH[7] EP8FIFOPFH[7] EP8FIFOPFL[7] EP8FIFOPFL[7] reserved EP2ISOINPKTS EP4ISOINPKTS EP6ISOINPKTS EP8ISOINPKTS reserved INPKTEND[7] OUTPKTEND[7] INTERRUPTS EP2FIFOIE[7] EP2FIFOIRQ EP4FIFOIE
[7,8]
Description ECC1 Byte 2 Address ECC2 Byte 0 Address ECC2 Byte 1 Address ECC2 Byte 2 Address Endpoint 2 / slave FIFO Programmable Flag H Endpoint 2 / slave FIFO Programmable Flag H Endpoint 2 / slave FIFO Programmable Flag L Endpoint 2 / slave FIFO Programmable Flag L Endpoint 4 / slave FIFO Programmable Flag H Endpoint 4 / slave FIFO Programmable Flag H Endpoint 4 / slave FIFO Programmable Flag L Endpoint 4 / slave FIFO Programmable Flag L Endpoint 6 / slave FIFO Programmable Flag H Endpoint 6 / slave FIFO Programmable Flag H Endpoint 6 / slave FIFO Programmable Flag L Endpoint 6 / slave FIFO Programmable Flag L Endpoint 8 / slave FIFO Programmable Flag H Endpoint 8 / slave FIFO Programmable Flag H Endpoint 8 / slave FIFO Programmable Flag L Endpoint 8 / slave FIFO Programmable Flag L EP2 (if ISO) IN Packets per frame (1-3) EP4 (if ISO) IN Packets per frame (1-3) EP6 (if ISO) IN Packets per frame (1-3) EP8 (if ISO) IN Packets per frame (1-3) Force IN Packet End Force OUT Packet End Endpoint 2 slave FIFO Flag Interrupt Enable Endpoint 2 slave FIFO Flag Interrupt Request Endpoint 4 slave FIFO Flag Interrupt Enable Endpoint 4 slave FIFO Flag Interrupt Request Endpoint 6 slave FIFO Flag Interrupt Enable Endpoint 6 slave FIFO Flag Interrupt Request Endpoint 8 slave FIFO Flag Interrupt Enable Endpoint 8 slave FIFO Flag Interrupt Request IN-BULK-NAK Interrupt Enable IN-BULK-NAK interrupt Request Endpoint Ping-NAK / IBN Interrupt Enable Endpoint Ping-NAK / IBN Interrupt Request USB Int Enables USB Interrupt Requests Endpoint Interrupt Enables
b7 COL5 LINE15 LINE7 COL5 DECIS DECIS PFC7 IN:PKTS[1] OUT:PFC7 DECIS DECIS PFC7
b6 COL4 LINE14 LINE6 COL4 PKTSTAT PKTSTAT PFC6 IN:PKTS[0] OUT:PFC6 PKTSTAT PKTSTAT PFC6
b5 COL3 LINE13 LINE5 COL3 IN:PKTS[2] OUT:PFC12 OUT:PFC12 PFC5 PFC5 0 0 PFC5
b4 COL2 LINE12 LINE4 COL2 IN:PKTS[1] OUT:PFC11 OUT:PFC11 PFC4 PFC4
b3 b2 COL1 COL0 LINE11 LINE10 LINE3 LINE2 COL1 COL0 IN:PKTS[0] 0 OUT:PFC10 OUT:PFC10 0 PFC3 PFC3 PFC2 PFC2
b1 LINE17 LINE9 LINE1 0 PFC9 PFC9 PFC1 PFC1 0 0 PFC1 PFC1 PFC9 PFC9 PFC1 PFC1 0 0 PFC1 PFC1
b0 LINE16 LINE8 LINE0 0 PFC8 IN:PKTS[2] OUT:PFC8 PFC0 PFC0 PFC8 PFC8 PFC0 PFC0 PFC8 IN:PKTS[2] OUT:PFC8 PFC0 PFC0 PFC8 PFC8 PFC0 PFC0
Default 00000000 00000000 00000000 00000000 10001000
Access R R R R bbbbbrbb
10001000 bbbbbrbb 00000000 RW 00000000 RW 10001000 bbrbbrrb 10001000 bbrbbrrb 00000000 RW 00000000 RW 00001000 bbbbbrbb 00001000 bbbbbrbb 00000000 RW 00000000 RW 00001000 bbrbbrrb 00001000 bbrbbrrb 00000000 RW 00000000 RW
IN: PKTS[1] IN: PKTS[0] 0 OUT:PFC10 OUT:PFC9 OUT:PFC10 OUT:PFC9 0 PFC4 PFC4 PFC3 PFC3 PFC2 PFC2
IN: PKTS[1] IN: PKTS[0] PFC5 OUT:PFC7 OUT:PFC6 DECIS PKTSTAT IN:PKTS[2] OUT:PFC12 DECIS PKTSTAT OUT:PFC12 PFC7 IN:PKTS[1] OUT:PFC7 DECIS DECIS PFC7 PFC6 IN:PKTS[0] OUT:PFC6 PKTSTAT PKTSTAT PFC6 PFC5 PFC5 0 0 PFC5
IN:PKTS[1] IN:PKTS[0] 0 OUT:PFC11 OUT:PFC10 OUT:PFC11 OUT:PFC10 0 PFC4 PFC4 PFC3 PFC3 PFC2 PFC2
IN: PKTS[1] IN: PKTS[0] 0 OUT:PFC10 OUT:PFC9 OUT:PFC10 OUT:PFC9 0 PFC4 PFC4 PFC3 PFC3 PFC2 PFC2
IN: PKTS[1] IN: PKTS[0] PFC5 OUT:PFC7 OUT:PFC6 AADJ AADJ AADJ AADJ 0 0 0 0 0 0 0 0
8 E640 1 E641 1 E642 1 E643 1 E644 4 E648 1 E649 7 E650 1 E651 1 E652 1 E653 1 E654 1 E655 1 E656 1 E657 1 E658 1 E659 1 E65A 1 E65B 1 E65C 1 E65D 1 E65E 1
0 0 0 0
0 0 0 0
0 0 0 0
INPPF1 INPPF1 INPPF1 INPPF1
INPPF0 INPPF0 INPPF0 INPPF0
00000001 brrrrrbb 00000001 brrrrrrr 00000001 brrrrrbb 00000001 brrrrrrr
Skip Skip 0 0 0 0 0 0 0 0 0 0 EP8 EP8 0 0 EP8
0 0 0 0 0 0 0 0 0 0 0 0 EP6 EP6 EP0ACK EP0ACK EP6
0 0 0 0 0 0 0 0 0 0 EP8 EP8 EP4 EP4 HSGRANT HSGRANT EP4
0 0 0 0 0 0 0 0 0 0 EP6 EP6 EP2 EP2 URES URES EP2
EP3 EP3 EDGEPF 0 EDGEPF 0 EDGEPF 0 EDGEPF 0 EP4 EP4 EP1 EP1 SUSP SUSP EP1OUT
EP2 EP2 PF PF PF PF PF PF PF PF EP2 EP2 EP0 EP0 SUTOK SUTOK EP1IN
EP1 EP1 EF EF EF EF EF EF EF EF EP1 EP1 0 0 SOF SOF EP0OUT
EP0 EP0 FF FF FF FF FF FF FF FF EP0 EP0 IBN IBN SUDAV SUDAV EP0IN
xxxxxxxx xxxxxxxx
W W
00000000 RW 00000000 rrrrrbbb 00000000 RW 00000000 rrrrrbbb 00000000 RW 00000000 rrrrrbbb 00000000 RW 00000000 rrrrrbbb 00000000 RW 00xxxxxx rrbbbbbb 00000000 RW xxxxxx0x bbbbbbrb 00000000 RW 0xxxxxxx rbbbbbbb 00000000 RW
[7] [7,8]
EP4FIFOIRQ
EP6FIFOIE[7] EP6FIFOIRQ EP8FIFOIE
[7,8]
[7] [7,8]
EP8FIFOIRQ IBNIE IBNIRQ NAKIE NAKIRQ[8] USBIE USBIRQ[8] EPIE
[8]
Note: 8. The register can only be reset, it cannot be set.
Document #: 001-04247 Rev. *A
Page 19 of 40
PRELIMINARY DRAFT CY7C68033/CY7C68034
Table 6-1. NX2LP-Flex Register Summary (continued)
Hex Size Name E65F 1 EPIRQ[8] E660 1 E661 1 E662 1 E663 1 E664 1 E665 1 E666 1 E667 1 E668 1 E669 7 E670 1 E671 1 E672 1 E673 E677 E678 E679 E67A E67B 4 1 1 1 1 1 GPIFIE[7] GPIFIRQ[7] USBERRIE USBERRIRQ[8] ERRCNTLIM CLRERRCNT INT2IVEC INT4IVEC INTSET-UP reserved INPUT / OUTPUT PORTACFG PORTCCFG PORTECFG XTALINSRC reserved I2CS I2DAT I2CTL XAUTODAT1 XAUTODAT2 UDMA CRC UDMACRCH[7] UDMACRCL[7] UDMACRCQUALIFIER USB CONTROL USBCS SUSPEND WAKEUPCS TOGCTL USBFRAMEH USBFRAMEL MICROFRAME FNADDR reserved ENDPOINTS EP0BCH[7] EP0BCL[7] reserved EP1OUTBC reserved EP1INBC EP2BCH[7] EP2BCL[7] reserved EP4BCH[7] EP4BCL[7] reserved EP6BCH[7] EP6BCL[7] reserved EP8BCH[7] EP8BCL[7] reserved EP0CS EP1OUTCS Endpoint 8 Byte Count H 0 Endpoint 8 Byte Count L BC7/SKIP Endpoint 0 Control and Status Endpoint 1 OUT Control and Status HSNAK 0 0 BC6 0 0 0 BC5 0 0 0 BC4 0 0 0 BC3 0 0 0 BC2 0 0 BC9 BC1 BUSY BUSY BC8 BC0 STALL STALL 000000xx RW xxxxxxxx RW 10000000 bbbbbbrb 00000000 bbbbbbrb Description b7 Endpoint Interrupt EP8 Requests GPIF Interrupt Enable 0 GPIF Interrupt Request 0 USB Error Interrupt ISOEP8 Enables USB Error Interrupt ISOEP8 Requests USB Error counter and EC3 limit Clear Error Counter EC3:0 x Interrupt 2 (USB) 0 Autovector Interrupt 4 (slave FIFO & 1 GPIF) Autovector Interrupt 2&4 set-up 0 b6 EP6 0 0 ISOEP6 ISOEP6 EC2 x I2V4 0 0 b5 EP4 0 0 ISOEP4 ISOEP4 EC1 x I2V3 I4V3 0 b4 EP2 0 0 ISOEP2 ISOEP2 EC0 x I2V2 I4V2 0 b3 EP1OUT 0 0 0 0 LIMIT3 x I2V1 I4V1 AV2EN b2 EP1IN 0 0 0 0 LIMIT2 x I2V0 I4V0 0 b1 EP0OUT GPIFWF GPIFWF 0 0 LIMIT1 x 0 0 INT4SRC b0 EP0IN Default 0 Access RW
GPIFDONE 00000000 RW GPIFDONE 000000xx RW ERRLIMIT 00000000 RW ERRLIMIT LIMIT0 x 0 0 AV4EN 0000000x bbbbrrrb xxxx0100 rrrrbbbb xxxxxxxx W 00000000 R 10000000 R 00000000 RW
I/O PORTA Alternate Configuration I/O PORTC Alternate Configuration I/O PORTE Alternate Configuration XTALIN Clock Source I2C Bus Control & Status I2C Bus Data I2C Bus Control Autoptr1 MOVX access, when APTREN=1 Autoptr2 MOVX access, when APTREN=1 UDMA CRC MSB UDMA CRC LSB UDMA CRC Qualifier
FLAGD GPIFA7 GPIFA8 0 START d7 0 D7 D7
SLCS GPIFA6 T2EX 0 STOP d6 0 D6 D6
0 GPIFA5 INT6 0 LASTRD d5 0 D5 D5
0 GPIFA4 RXD1OUT 0 ID1 d4 0 D4 D4
0 GPIFA3
0 GPIFA2
INT1 GPIFA1 T1OUT 0 ACK d1 STOPIE D1 D1
INT0 GPIFA0 T0OUT EXTCLK DONE d0 400kHz D0 D0
00000000 RW 00000000 RW 00000000 RW 00000000 rrrrrrrb 000xx000 xxxxxxxx 00000000 xxxxxxxx xxxxxxxx bbbrrrrr RW RW RW RW
RXD0OUT T2OUT 0 ID0 d3 0 D3 D3 0 BERR d2 0 D2 D2
E67C 1
E67D 1 E67E 1 E67F 1
CRC15 CRC7 QENABLE
CRC14 CRC6 0
CRC13 CRC5 0
CRC12 CRC4 0
CRC11 CRC3 QSTATE
CRC10 CRC2 QSIGNAL2
CRC9 CRC1 QSIGNAL1
CRC8 CRC0 QSIGNAL0
01001010 RW 10111010 RW 00000000 brrrbbbb
E680 E681 E682 E683 E684 E685 E686 E687 E688
1 1 1 1 1 1 1 1 2
USB Control & Status Put chip into suspend Wakeup Control & Status Toggle Control USB Frame count H USB Frame count L Microframe count, 0-7 USB Function address
HSM x WU2 Q 0 FC7 0 0
0 x WU S 0 FC6 0 FA6
0 x WU2POL R 0 FC5 0 FA5
0 x WUPOL IO 0 FC4 0 FA4
DISCON x 0 EP3 0 FC3 0 FA3
NOSYNSOF x DPEN EP2 FC10 FC2 MF2 FA2
RENUM x WU2EN EP1 FC9 FC1 MF1 FA1
SIGRSUME x WUEN EP0 FC8 FC0 MF0 FA0
x0000000 xxxxxxxx xx000101 x0000000 00000xxx xxxxxxxx 00000xxx 0xxxxxxx
rrrrbbbb W bbbbrbbb rrrbbbbb R R R R
E68A E68B E68C E68D E68E E68F E690 E691 E692 E694 E695 E696 E698 E699 E69C E69D E69E E6A0
1 1 1 1 1 1 1 1 2 1 1 2 1 1 1 1 2 1
Endpoint 0 Byte Count H (BC15) Endpoint 0 Byte Count L (BC7) Endpoint 1 OUT Byte Count 0
(BC14) BC6 BC6
(BC13) BC5 BC5
(BC12) BC4 BC4
(BC11) BC3 BC3
(BC10) BC2 BC2
(BC9) BC1 BC1
(BC8) BC0 BC0
xxxxxxxx xxxxxxxx
RW RW
0xxxxxxx RW
Endpoint 1 IN Byte Count 0 Endpoint 2 Byte Count H 0 Endpoint 2 Byte Count L BC7/SKIP Endpoint 4 Byte Count H 0 Endpoint 4 Byte Count L BC7/SKIP Endpoint 6 Byte Count H 0 Endpoint 6 Byte Count L BC7/SKIP
BC6 0 BC6 0 BC6 0 BC6
BC5 0 BC5 0 BC5 0 BC5
BC4 0 BC4 0 BC4 0 BC4
BC3 0 BC3 0 BC3 0 BC3
BC2 BC10 BC2 0 BC2 BC10 BC2
BC1 BC9 BC1 BC9 BC1 BC9 BC1
BC0 BC8 BC0 BC8 BC0 BC8 BC0
0xxxxxxx RW 00000xxx RW xxxxxxxx RW 000000xx RW xxxxxxxx RW 00000xxx RW xxxxxxxx RW
E69A 2
E6A1 1
Document #: 001-04247 Rev. *A
Page 20 of 40
PRELIMINARY DRAFT CY7C68033/CY7C68034
Table 6-1. NX2LP-Flex Register Summary (continued)
Hex Size Name E6A2 1 EP1INCS E6A3 1 E6A4 1 E6A5 1 E6A6 1 E6A7 1 E6A8 1 E6A9 1 E6AA 1 E6AB 1 E6AC 1 E6AD 1 E6AE 1 E6AF 1 E6B0 1 E6B1 1 E6B2 1 E6B3 1 E6B4 1 E6B5 1 2 E6B8 8 EP2CS EP4CS EP6CS EP8CS EP2FIFOFLGS EP4FIFOFLGS EP6FIFOFLGS EP8FIFOFLGS EP2FIFOBCH EP2FIFOBCL EP4FIFOBCH EP4FIFOBCL EP6FIFOBCH EP6FIFOBCL EP8FIFOBCH EP8FIFOBCL SUDPTRH SUDPTRL SUDPTRCTL reserved SET-UPDAT Description Endpoint 1 IN Control and Status Endpoint 2 Control and Status Endpoint 4 Control and Status Endpoint 6 Control and Status Endpoint 8 Control and Status Endpoint 2 slave FIFO Flags Endpoint 4 slave FIFO Flags Endpoint 6 slave FIFO Flags Endpoint 8 slave FIFO Flags Endpoint 2 slave FIFO total byte count H Endpoint 2 slave FIFO total byte count L Endpoint 4 slave FIFO total byte count H Endpoint 4 slave FIFO total byte count L Endpoint 6 slave FIFO total byte count H Endpoint 6 slave FIFO total byte count L Endpoint 8 slave FIFO total byte count H Endpoint 8 slave FIFO total byte count L Set-up Data Pointer high address byte Set-up Data Pointer low address byte Set-up Data Pointer Auto Mode b7 0 0 0 0 0 0 0 0 0 0 BC7 0 BC7 0 BC7 0 BC7 A15 A7 0 b6 0 NPAK2 0 NPAK2 0 0 0 0 0 0 BC6 0 BC6 0 BC6 0 BC6 A14 A6 0 b5 0 NPAK1 NPAK1 NPAK1 NPAK1 0 0 0 0 0 BC5 0 BC5 0 BC5 0 BC5 A13 A5 0 b4 0 NPAK0 NPAK0 NPAK0 NPAK0 0 0 0 0 BC12 BC4 0 BC4 0 BC4 0 BC4 A12 A4 0 b3 0 FULL FULL FULL FULL 0 0 0 0 BC11 BC3 0 BC3 BC11 BC3 0 BC3 A11 A3 0 b2 0 EMPTY EMPTY EMPTY EMPTY PF PF PF PF BC10 BC2 BC10 BC2 BC10 BC2 BC10 BC2 A10 A2 0 b1 BUSY 0 0 0 0 EF EF EF EF BC9 BC1 BC9 BC1 BC9 BC1 BC9 BC1 A9 A1 0 b0 STALL STALL STALL STALL STALL FF FF FF FF BC8 BC0 BC8 BC0 BC8 BC0 BC8 BC0 A8 0 SDPAUTO Default Access 00000000 bbbbbbrb 00101000 rrrrrrrb 00101000 rrrrrrrb 00000100 rrrrrrrb 00000100 rrrrrrrb 00000010 R 00000010 R 00000110 R 00000110 R 00000000 R 00000000 R 00000000 R 00000000 R 00000000 R 00000000 R 00000000 R 00000000 R xxxxxxxx RW
xxxxxxx0 bbbbbbbr 00000001 RW
8 bytes of set-up data D7 SET-UPDAT[0] = bmRequestType SET-UPDAT[1] = bmRequest SET-UPDAT[2:3] = wValue SET-UPDAT[4:5] = wIndex SET-UPDAT[6:7] = wLength Waveform Selector GPIF Done, GPIF IDLE drive mode Inactive Bus, CTL states CTL Drive Type GPIF Address H GPIF Address L Flowstate Enable and Selector Flowstate Logic CTL-Pin States in Flowstate (when Logic = 0) CTL-Pin States in Flowstate (when Logic = 1) Holdoff Configuration
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
E6C0 1 E6C1 1 E6C2 E6C3 E6C4 E6C5 1 1 1 1
GPIF GPIFWFSELECT GPIFIDLECS GPIFIDLECTL GPIFCTLCFG GPIFADRH[7] GPIFADRL[7] FLOWSTATE FLOWSTATE FLOWLOGIC FLOWEQ0CTL
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 DONE 0 0 0 0 0 TRICTL 0 GPIFA7 FSE LFUNC1 CTL0E3 0 0 0 GPIFA6 0 LFUNC0 CTL0E2 CTL5 CTL5 0 GPIFA5 0 TERMA2 CTL0E1/ CTL5 CTL4 CTL4 0 GPIFA4 0 TERMA1 CTL0E0/ CTL4 CTL3 CTL3 0 GPIFA3 0 TERMA0 CTL3
FIFOWR0 0 CTL2 CTL2 0 GPIFA2 FS2 TERMB2 CTL2
FIFORD1 0 CTL1 CTL1 0 GPIFA1 FS1 TERMB1 CTL1
FIFORD0 IDLEDRV CTL0 CTL0 GPIFA8 GPIFA0 FS0 TERMB0 CTL0
11100100 RW 10000000 RW 11111111 00000000 00000000 00000000 RW RW RW RW
E6C6 1 E6C7 1 E6C8 1
00000000 brrrrbbb 00000000 RW 00000000 RW
E6C9 1 E6CA 1 E6CB 1 E6CC 1 E6CD 1 E6CE 1 E6CF 1
FLOWEQ1CTL FLOWHOLDOFF FLOWSTB FLOWSTBEDGE FLOWSTBPERIOD GPIFTCB3[7] GPIFTCB2[7]
Flowstate Strobe Configuration Flowstate Rising/Falling 0 Edge Configuration Master-Strobe Half-Period D7 GPIF Transaction Count TC31 Byte 3 GPIF Transaction Count TC23 Byte 2
CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE 0 SLAVE RDYASYNC CTLTOGL SUSTAIN 0 0 D6 TC30 TC22 0 D5 TC29 TC21 0 D4 TC28 TC20 0 D3 TC27 TC19
CTL0E3
CTL0E2
CTL2 HOCTL2 MSTB2 0 D2 TC26 TC18
CTL1 HOCTL1 MSTB1 FALLING D1 TC25 TC17
CTL0 HOCTL0 MSTB0 RISING D0 TC24 TC16
00000000 RW 00010010 RW 00100000 RW 00000001 rrrrrrbb 00000010 RW 00000000 RW 00000000 RW
Document #: 001-04247 Rev. *A
Page 21 of 40
PRELIMINARY DRAFT CY7C68033/CY7C68034
Table 6-1. NX2LP-Flex Register Summary (continued)
Hex Size Name E6D0 1 GPIFTCB1[7] E6D1 1 2 GPIFTCB0[7] Description b7 GPIF Transaction Count TC15 Byte 1 GPIF Transaction Count TC7 Byte 0 b6 TC14 TC6 b5 TC13 TC5 b4 TC12 TC4 b3 TC11 TC3 b2 TC10 TC2 b1 TC9 TC1 b0 TC8 TC0 Default Access 00000000 RW 00000001 RW 00000000 RW
E6D2 1 E6D3 1 E6D4 1 3
E6DA 1 E6DB 1 E6DC 1 3
E6E2 1 E6E3 1 E6E4 1 3
E6EA 1 E6EB 1 E6EC 1 3 E6F0 1 E6F1 1 E6F2 1 E6F3 1
reserved reserved reserved EP2GPIFFLGSEL[7] Endpoint 2 GPIF Flag select EP2GPIFPFSTOP Endpoint 2 GPIF stop transaction on prog. flag EP2GPIFTRIG[7] Endpoint 2 GPIF Trigger reserved reserved reserved EP4GPIFFLGSEL[7] Endpoint 4 GPIF Flag select EP4GPIFPFSTOP Endpoint 4 GPIF stop transaction on GPIF Flag EP4GPIFTRIG[7] Endpoint 4 GPIF Trigger reserved reserved reserved EP6GPIFFLGSEL[7] Endpoint 6 GPIF Flag select EP6GPIFPFSTOP Endpoint 6 GPIF stop transaction on prog. flag EP6GPIFTRIG[7] Endpoint 6 GPIF Trigger reserved reserved reserved EP8GPIFFLGSEL[7] Endpoint 8 GPIF Flag select EP8GPIFPFSTOP Endpoint 8 GPIF stop transaction on prog. flag EP8GPIFTRIG[7] Endpoint 8 GPIF Trigger reserved XGPIFSGLDATH GPIF Data H (16-bit mode only) XGPIFSGLDATLX Read/Write GPIF Data L & trigger transaction XGPIFSGLDATLRead GPIF Data L, no NOX transaction trigger GPIFREADYCFG Internal RDY, Sync/Async, RDY pin states
0 0 x
0 0 x
0 0 x
0 0 x
0 0 x
0 0 x
FS1 0 x
FS0
00000000 RW
FIFO2FLAG 00000000 RW x xxxxxxxx W
0 0 x
0 0 x
0 0 x
0 0 x
0 0 x
0 0 x
FS1 0 x
FS0
00000000 RW
FIFO4FLAG 00000000 RW x xxxxxxxx W
0 0 x
0 0 x
0 0 x
0 0 x
0 0 x
0 0 x
FS1 0 x
FS0
00000000 RW
FIFO6FLAG 00000000 RW x xxxxxxxx W
0 0 x D15 D7 D7 INTRDY
0 0 x D14 D6 D6 SAS
0 0 x D13 D5 D5 TCXRDY5
0 0 x D12 D4 D4 0
0 0 x D11 D3 D3 0
0 0 x D10 D2 D2 0
FS1 0 x D9 D1 D1 0
FS0
00000000 RW
FIFO8FLAG 00000000 RW x D8 D0 D0 0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx W RW RW R
00000000 bbbrrrrr
E6F4 1 E6F5 1 E6F6 2 E740 E780 E7C0 F000
F400 F600 F800
FC00 FE00 xxxx
GPIFREADYSTAT GPIF Ready Status GPIFABORT Abort GPIF Waveforms reserved ENDPOINT BUFFERS 64 EP0BUF EP0-IN/-OUT buffer 64 EP10UTBUF EP1-OUT buffer 64 EP1INBUF EP1-IN buffer 2048 reserved 1024 EP2FIFOBUF 512/1024-byte EP 2 / slave FIFO buffer (IN or OUT) 512 EP4FIFOBUF 512 byte EP 4 / slave FIFO buffer (IN or OUT) 512 reserved 1024 EP6FIFOBUF 512/1024-byte EP 6 / slave FIFO buffer (IN or OUT) 512 EP8FIFOBUF 512 byte EP 8 / slave FIFO buffer (IN or OUT) 512 reserved IC Configuration Byte Special Function Registers (SFRs) IOA[9] Port A (bit addressable) SP Stack Pointer DPL0 Data Pointer 0 L DPH0 Data Pointer 0 H
0 x
0 x
RDY5 x
RDY4 x
RDY3 x
RDY2 x
RDY1 x
RDY0 x
00xxxxxx R xxxxxxxx W
D7 D7 D7 D7
D6 D6 D6 D6
D5 D5 D5 D5
D4 D4 D4 D4
D3 D3 D3 D3
D2 D2 D2 D2
D1 D1 D1 D1
D0 D0 D0 D0
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
RW RW RW RW RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
0
DISCON
0
0
0
0
0
400KHZ
xxxxxxxx
[10]
n/a
80 81 82 83
1 1 1 1
D7 D7 A7 A15
D6 D6 A6 A14
D5 D5 A5 A13
D4 D4 A4 A12
D3 D3 A3 A11
D2 D2 A2 A10
D1 D1 A1 A9
D0 D0 A0 A8
xxxxxxxx 00000111 00000000 00000000
RW RW RW RW
Notes: 9. SFRs not part of the standard 8051 architecture. 10. If no NAND is detected by the SIE then the default is 00000000.
Document #: 001-04247 Rev. *A
Page 22 of 40
PRELIMINARY DRAFT CY7C68033/CY7C68034
Table 6-1. NX2LP-Flex Register Summary (continued)
Hex 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A8 A9 AA AB AC AD AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C8 C9 CA Size 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 1 1 1 Name DPL1[9] DPH1[9] DPS[9] PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON[9] reserved IOB[9] EXIF[9] MPAGE[9] reserved SCON0 SBUF0 AUTOPTRH1[9] AUTOPTRL1[9] reserved AUTOPTRH2[9] AUTOPTRL2[9] reserved IOC[9] INT2CLR[9] INT4CLR[9] reserved IE reserved EP2468STAT[9] EP24FIFOFLGS
[9] [9]
Description Data Pointer 1 L Data Pointer 1 H Data Pointer 0/1 select Power Control Timer/Counter Control (bit addressable) Timer/Counter Mode Control Timer 0 reload L Timer 1 reload L Timer 0 reload H Timer 1 reload H Clock Control
b7 A7 A15 0 SMOD0 TF1 GATE D7 D7 D15 D15 x
b6 A6 A14 0 x TR1 CT D6 D6 D14 D14 x D6 IE4 A14
b5 A5 A13 0 1 TF0 M1 D5 D5 D13 D13 T2M D5 ICINT A13
b4 A4 A12 0 1 TR0 M0 D4 D4 D12 D12 T1M D4 USBNT A12
b3 A3 A11 0 x IE1 GATE D3 D3 D11 D11 T0M D3 1 A11
b2 A2 A10 0 x IT1 CT D2 D2 D10 D10 MD2 D2 0 A10
b1 A1 A9 0 x IE0 M1 D1 D1 D9 D9 MD1 D1 0 A9
b0 A0 A8 SEL IDLE IT0 M0 D0 D0 D8 D8 MD0 D0 0 A8
Default 00000000 00000000 00000000 00110000 00000000
Access RW RW RW RW RW
00000000 RW 00000000 00000000 00000000 00000000 00000001 RW RW RW RW RW
Port B (bit addressable) D7 External Interrupt Flag(s) IE5 Upper Addr Byte of MOVX A15 using @R0 / @R1 Serial Port 0 Control (bit addressable) Serial Port 0 Data Buffer Autopointer 1 Address H Autopointer 1 Address L SM0_0 D7 A15 A7
xxxxxxxx RW 00001000 RW 00000000 RW
SM1_0 D6 A14 A6 A14 A6 D6 x x ES1
SM2_0 D5 A13 A5 A13 A5 D5 x x ET2
REN_0 D4 A12 A4 A12 A4 D4 x x ES0
TB8_0 D3 A11 A3 A11 A3 D3 x x ET1
RB8_0 D2 A10 A2 A10 A2 D2 x x EX1
TI_0 D1 A9 A1 A9 A1 D1 x x ET0
RI_0 D0 A8 A0 A8 A0 D0 x x EX0
00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW xxxxxxxx xxxxxxxx xxxxxxxx RW W W
Autopointer 2 Address H A15 Autopointer 2 Address L A7 Port C (bit addressable) Interrupt 2 clear Interrupt 4 clear Interrupt Enable (bit addressable) D7 x x EA
00000000 RW
EP68FIFOFLGS
Endpoint 2,4,6,8 status EP8F flags Endpoint 2,4 slave FIFO 0 status flags Endpoint 6,8 slave FIFO 0 status flags 0 D7 D7 D7 D7 D7 D7 D7 1
EP8E EP4PF EP8PF
EP6F EP4EF EP8EF
EP6E EP4FF EP8FF
EP4F 0 0
EP4E EP2PF EP6PF
EP2F EP2EF EP6EF
EP2E EP2FF EP6FF
01011010 R 00100010 R 01100110 R
reserved AUTOPTRSET-UP[9] Autopointer 1&2 set-up IOD[9] Port D (bit addressable) IOE[9] Port E (NOT bit addressable) [9] OEA Port A Output Enable [9] OEB Port B Output Enable OEC[9] Port C Output Enable OED[9] Port D Output Enable OEE[9] Port E Output Enable reserved IP Interrupt Priority (bit addressable) reserved EP01STAT[9] Endpoint 0&1 Status GPIFTRIG
[9, 7]
0 D6 D6 D6 D6 D6 D6 D6 PS1
0 D5 D5 D5 D5 D5 D5 D5 PT2
0 D4 D4 D4 D4 D4 D4 D4 PS0
0 D3 D3 D3 D3 D3 D3 D3 PT1
APTR2INC D2 D2 D2 D2 D2 D2 D2 PX1
APTR1INC D1 D1 D1 D1 D1 D1 D1 PT0
APTREN D0 D0 D0 D0 D0 D0 D0 PX0
00000110 RW xxxxxxxx RW xxxxxxxx RW 00000000 00000000 00000000 00000000 00000000 RW RW RW RW RW
10000000 RW
0 DONE
0 0
0 0
0 0
0 0
EP1INBSY RW
Endpoint 2,4,6,8 GPIF slave FIFO Trigger
EP1OUTBS EP0BSY Y EP1 EP0
00000000 R 10000xxx brrrrbbb
reserved GPIFSGLDATH[9] GPIFSGLDATLX GPIFSGLDAT LNOX[9] SCON1[9] SBUF1[9] reserved T2CON reserved RCAP2L
[9]
GPIF Data H (16-bit mode D15 only) GPIF Data L w/ Trigger D7 GPIF Data L w/ No Trigger D7 Serial Port 1 Control (bit SM0_1 addressable) Serial Port 1 Data Buffer D7 Timer/Counter 2 Control (bit addressable) TF2
D14 D6 D6 SM1_1 D6 EXF2
D13 D5 D5 SM2_1 D5 RCLK
D12 D4 D4 REN_1 D4 TCLK
D11 D3 D3 TB8_1 D3 EXEN2
D10 D2 D2 RB8_1 D2 TR2
D9 D1 D1 TI_1 D1 CT2
D8 D0 D0 RI_1 D0 CPRL2
xxxxxxxx xxxxxxxx xxxxxxxx
RW RW R
00000000 RW 00000000 RW 00000000 RW
Capture for Timer 2, auto- D7 reload, up-counter
D6
D5
D4
D3
D2
D1
D0
00000000 RW
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PRELIMINARY DRAFT CY7C68033/CY7C68034
Table 6-1. NX2LP-Flex Register Summary (continued)
Hex CB CC CD CE D0 D1 D8 D9 E0 E1 E8 E9 F0 F1 F8 F9 Size Name 1 1 1 2 1 7 1 7 1 7 1 7 1 7 1 7 RCAP2H TL2 TH2 reserved PSW reserved EICON[9] reserved ACC reserved EIE[9] reserved B reserved EIP[9] reserved Description b7 b6 D6 D6 D14 AC b5 D5 D5 D13 F0 b4 D4 D4 D12 RS1 b3 D3 D3 D11 RS0 b2 D2 D2 D10 OV b1 D1 D1 D9 F1 b0 D0 D0 D8 P Default Access
Capture for Timer 2, auto- D7 reload, up-counter Timer 2 reload L D7 Timer 2 reload H D15 Program Status Word (bit CY addressable) External Interrupt Control SMOD1 Accumulator (bit address- D7 able) External Interrupt Enable(s) B (bit addressable) 1
00000000 RW 00000000 RW 00000000 RW 00000000 RW
1 D6
ERESI D5
RESI D4
INT6 D3
0 D2
0 D1
0 D0
01000000 RW 00000000 RW
1
1
EX6
EX5
EX4
EIC
EUSB
11100000 RW
D7
D6 1
D5 1
D4 PX6
D3 PX5
D2 PX4
D1 PIC
D0 PUSB
00000000 RW 11100000 RW
External Interrupt Priority 1 Control
R = all bits read-only W = all bits write-only
r = read-only bit w = write-only bit b = both read/write bit
7.0
Absolute Maximum Ratings
8.0
Operating Conditions
Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Supplied ...... 0C to +70C Supply Voltage to Ground Potential ............... -0.5V to +4.0V DC Input Voltage to Any Input Pin ........................ +5.25V[11] DC Voltage Applied to Outputs in High Z State......................... -0.5V to VCC + 0.5V Power Dissipation .....................................................300 mW Static Discharge Voltage ...........................................> 2000V Max Output Current, per I/O port .................................10 mA
Note: 11. Applying power to I/O pins when the chip is not powered is not recommended.
TA (Ambient Temperature Under Bias) ............. 0C to +70C Supply Voltage ...........................................+3.15V to +3.45V Ground Voltage ................................................................. 0V FOSC (Oscillator or Crystal Frequency) ... 24 MHz 100 ppm (Parallel Resonant)
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PRELIMINARY DRAFT CY7C68033/CY7C68034
9.0 DC Characteristics
Description Supply Voltage Input HIGH Voltage Input LOW Voltage Crystal Input HIGH Voltage Crystal Input LOW Voltage Input Leakage Current Output Voltage HIGH Output LOW Voltage Output Current HIGH Output Current LOW Input Pin Capacitance Suspend Current CY7C68034 Suspend Current CY7C68033 ICC IUNCONFIG TRESET Supply Current Unconfigured Current Reset Time After Valid Power Pin Reset After powered on Except D+/D- D+/D- ISUSP Connected Disconnected Connected Disconnected 8051 running, connected to USB HS 8051 running, connected to USB FS Before bMaxPower granted by host VCC min = 3.0V 5.0 200 300 100 0.5 0.3 43 35 43 0< VIN < VCC IOUT = 4 mA IOUT = -4 mA 2.4 0.4 4 4 10 15 380[12] 150[12] 1.2[12] 1.0[12] Conditions Min. 3.15 200 2 -0.5 2 -0.5 5.25 0.8 5.25 0.8 10 Typ. 3.3 Max. 3.45 Unit V s V V V V A V V mA mA pF pF A A mA mA mA mA mA mS S
Table 9-1. DC Characteristics Parameter VCC VIH VIL VIH_X VIL_X II VOH VOL IOH IOL CIN VCC Ramp Up 0 to 3.3V
9.1
USB Transceiver
USB 2.0-compliant in full- and high-speed modes.
10.0
10.1
AC Electrical Characteristics
USB Transceiver
USB 2.0-compliant in full- and high-speed modes.
Note: 12. Measured at Max VCC, 25C.
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PRELIMINARY DRAFT CY7C68033/CY7C68034
10.2 GPIF Synchronous Signals
tIFCLK IFCLK tSGA GPIFADR[8:0]
RDYX tSRY tRYH DATA(input) tSGD valid tDAH
CTLX
tXCTL DATA(output) N tXGD N+1
Figure 10-1. GPIF Synchronous Signals Timing Diagram[13] Table 10-1. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[13, 14] Parameter tIFCLK tSRY tRYH tSGD tDAH tSGA tXGD tXCTL IFCLK Period RDYX to Clock Set-up Time Clock to RDYX GPIF Data to Clock Set-up Time GPIF Data Hold Time Clock to GPIF Address Propagation Delay Clock to GPIF Data Output Propagation Delay Clock to CTLX Output Propagation Delay Description Min. 20.83 8.9 0 9.2 0 7.5 11 6.7 Max. Unit ns ns ns ns ns ns ns ns
Table 10-2. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[14] Parameter tIFCLK tSRY tRYH tSGD tDAH tSGA tXGD IFCLK Period[15] RDYX to Clock Set-up Time Clock to RDYX GPIF Data to Clock Set-up Time GPIF Data Hold Time Clock to GPIF Address Propagation Delay Clock to GPIF Data Output Propagation Delay Description Min. 20.83 2.9 3.7 3.2 4.5 11.5 15 10.7 Max. 200 Unit ns ns ns ns ns ns ns ns
tXCTL Clock to CTLX Output Propagation Delay Notes: 13. Dashed lines denote signals with programmable polarity. 14. GPIF asynchronous RDYx signals have a minimum Set-up time of 50 ns when using internal 48-MHz IFCLK. 15. IFCLK must not exceed 48 MHz.
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PRELIMINARY DRAFT CY7C68033/CY7C68034
10.3 Slave FIFO Synchronous Read
tIFCLK
IFCLK tSRD SLRD tXFLG FLAGS tRDH
DATA tOEon SLOE
N
N+1 tXFD tOEoff
Figure 10-2. Slave FIFO Synchronous Read Timing Diagram[13] Table 10-3. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[14] Parameter tIFCLK tSRD tRDH tOEon tOEoff tXFLG tXFD IFCLK Period SLRD to Clock Set-up Time Clock to SLRD Hold Time SLOE Turn-on to FIFO Data Valid SLOE Turn-off to FIFO Data Hold Clock to FLAGS Output Propagation Delay Clock to FIFO Data Output Propagation Delay Description Min. 20.83 18.7 0 10.5 10.5 9.5 11 Max. Unit ns ns ns ns ns ns ns
Table 10-4. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[14] Parameter tIFCLK tSRD tRDH tOEon tOEoff tXFLG tXFD IFCLK Period SLRD to Clock Set-up Time Clock to SLRD Hold Time SLOE Turn-on to FIFO Data Valid SLOE Turn-off to FIFO Data Hold Clock to FLAGS Output Propagation Delay Clock to FIFO Data Output Propagation Delay Description Min. 20.83 12.7 3.7 10.5 10.5 13.5 15 Max. 200 Unit ns ns ns ns ns ns ns
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PRELIMINARY DRAFT CY7C68033/CY7C68034
10.4 Slave FIFO Asynchronous Read
tRDpwh SLRD tRDpwl tXFLG FLAGS tXFD
DATA
N tOEon
N+1 tOEoff
SLOE
Figure 10-3. Slave FIFO Asynchronous Read Timing Diagram[13] Table 10-5. Slave FIFO Asynchronous Read Parameters[16] Parameter tRDpwl tRDpwh tXFLG tXFD tOEon tOEoff Description SLRD Pulse Width LOW SLRD Pulse Width HIGH SLRD to FLAGS Output Propagation Delay SLRD to FIFO Data Output Propagation Delay SLOE Turn-on to FIFO Data Valid SLOE Turn-off to FIFO Data Hold Min. 50 50 70 15 10.5 10.5 Max. Unit ns ns ns ns ns ns
Note: 16. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
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10.5 Slave FIFO Synchronous Write
tIFCLK IFCLK
SLWR
tSWR
tWRH
DATA
Z tSFD
N tFDH
Z
FLAGS tXFLG
Figure 10-4. Slave FIFO Synchronous Write Timing Diagram[13] Table 10-6. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[14] Parameter tIFCLK tSWR tWRH tSFD tFDH tXFLG IFCLK Period SLWR to Clock Set-up Time Clock to SLWR Hold Time FIFO Data to Clock Set-up Time Clock to FIFO Data Hold Time Clock to FLAGS Output Propagation Time Description Min. 20.83 18.1 0 9.2 0 9.5 Max. Unit ns ns ns ns ns ns
Table 10-7. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[14] Parameter tIFCLK tSWR tWRH tSFD tFDH tXFLG IFCLK Period SLWR to Clock Set-up Time Clock to SLWR Hold Time FIFO Data to Clock Set-up Time Clock to FIFO Data Hold Time Clock to FLAGS Output Propagation Time Description Min. 20.83 12.1 3.6 3.2 4.5 13.5 Max. 200 Unit ns ns ns ns ns ns
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PRELIMINARY DRAFT CY7C68033/CY7C68034
10.6 Slave FIFO Asynchronous Write
tWRpwh SLWR/SLCS# tWRpwl
tSFD DATA
tFDH
FLAGS
tXFD
Figure 10-5. Slave FIFO Asynchronous Write Timing Diagram[13] Table 10-8. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [16] Parameter tWRpwl tWRpwh tSFD tFDH tXFD SLWR Pulse LOW SLWR Pulse HIGH SLWR to FIFO DATA Set-up Time FIFO DATA to SLWR Hold Time SLWR to FLAGS Output Propagation Delay Description Min. 50 70 10 10 70 Max. Unit ns ns ns ns ns
10.7
Slave FIFO Synchronous Packet End Strobe
IFCLK tPEH PKTEND tSPE
FLAGS tXFLG
Figure 10-6. Slave FIFO Synchronous Packet End Strobe Timing Diagram[13] Table 10-9. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK [14] Parameter tIFCLK tSPE tPEH tXFLG IFCLK Period PKTEND to Clock Set-up Time Clock to PKTEND Hold Time Clock to FLAGS Output Propagation Delay Description Min. 20.83 14.6 0 9.5 Max. Unit ns ns ns ns
Table 10-10. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK [14] Parameter tIFCLK tSPE tPEH tXFLG IFCLK Period PKTEND to Clock Set-up Time Clock to PKTEND Hold Time Clock to FLAGS Output Propagation Delay Description Min. 20.83 8.6 2.5 13.5 Max. 200 Unit ns ns ns ns
There is no specific timing requirement that needs to be met for asserting PKTEND pin with regards to asserting SLWR. PKTEND can be asserted with the last data value clocked into
the FIFOs or thereafter. The only consideration is the set-up time tSPE and the hold time tPEH must be met. Although there are no specific timing requirements for the PKTEND assertion, there is a specific corner case condition Page 30 of 40
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PRELIMINARY DRAFT CY7C68033/CY7C68034
that needs attention while using the PKTEND to commit a one byte/word packet. There is an additional timing requirement that needs to be met when the FIFO is configured to operate in auto mode and it is desired to send two packets back to back: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word packet committed manually using the PKTEND pin. In this particular scenario, user must make sure to assert PKTEND at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet. Figure 10-7 below shows this scenario. X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode. Figure 10-7 shows a scenario where two packets are being committed. The first packet gets committed automatically when the number of bytes in the FIFO reaches X (value set in AUTOINLEN register) and the second one byte/word short packet being committed manually using PKTEND. Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet (causing the packet to be committed automatically). Not adhering to this timing will result in the NX2LP-Flex failing to send the one byte/word short packet.
tIFCLK
IFCLK
tSFA tFAH
FIFOADR
>= tSWR >= tWRH
SLWR
tSFD
tFDH
tSFD X-3
tFDH
tSFD X-2
tFDH
tSFD X-1
tFDH
tSFD X
tFDH
tSFD 1
tFDH
DATA
X-4
At least one IFCLK cycle
tSPE
tPEH
PKTEND
Figure 10-7. Slave FIFO Synchronous Write Sequence and Timing Diagram[13]
10.8
Slave FIFO Asynchronous Packet End Strobe
tPEpwh PKTEND tPEpwl
FLAGS tXFLG
Figure 10-8. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[13] Table 10-11. Slave FIFO Asynchronous Packet End Strobe Parameters[16] Parameter tPEpwl tPWpwh tXFLG Description PKTEND Pulse Width LOW PKTEND Pulse Width HIGH PKTEND to FLAGS Output Propagation Delay Min. 50 50 115 Max. Unit ns ns ns
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10.9 Slave FIFO Output Enable
SLOE tOEoff
DATA
tOEon
Figure 10-9. Slave FIFO Output Enable Timing Diagram[13] Table 10-12. Slave FIFO Output Enable Parameters Parameter tOEon tOEoff Description SLOE Assert to FIFO DATA Output SLOE Deassert to FIFO DATA Hold Min. Max. 10.5 10.5 Unit ns ns
10.10
Slave FIFO Address to Flags/Data
FIFOADR [1.0] tXFLG FLAGS tXFD DATA N N+1
Figure 10-10. Slave FIFO Address to Flags/Data Timing Diagram[13] Table 10-13. Slave FIFO Address to Flags/Data Parameters Parameter tXFLG tXFD Description FIFOADR[1:0] to FLAGS Output Propagation Delay FIFOADR[1:0] to FIFODATA Output Propagation Delay Min. Max. 10.7 14.3 Unit ns ns
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PRELIMINARY DRAFT CY7C68033/CY7C68034
10.11 Slave FIFO Synchronous Address
IFCLK
SLCS/FIFOADR [1:0] tSFA tFAH
Figure 10-11. Slave FIFO Synchronous Address Timing Diagram[13] Table 10-14. Slave FIFO Synchronous Address Parameters[14] Parameter tIFCLK tSFA tFAH Description Interface Clock Period FIFOADR[1:0] to Clock Set-up Time Clock to FIFOADR[1:0] Hold Time Min. 20.83 25 10 Max. 200 Unit ns ns ns
10.12
Slave FIFO Asynchronous Address
SLCS/FIFOADR [1:0] tSFA SLRD/SLWR/PKTEND tFAH
Figure 10-12. Slave FIFO Asynchronous Address Timing Diagram[13] Slave FIFO Asynchronous Address Parameters[16] Parameter tSFA tFAH Description FIFOADR[1:0] to SLRD/SLWR/PKTEND Set-up Time RD/WR/PKTEND to FIFOADR[1:0] Hold Time Min. 10 10 Max. Unit ns ns
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10.13 Sequence Diagram
10.13.1 Single and Burst Synchronous Read Example
tIFCLK
IFCLK
tSFA tFAH tSFA tFAH
FIFOADR
t=0
tSRD
tRDH
T=0
>= tSRD
>= tRDH
SLRD
t=2 t=3 T=2 T=3
SLCS
tXFLG
FLAGS
tXFD tXFD N+1 tOEoff tOEon N+1 N+2 tXFD N+3 tXFD N+4
DATA
Data Driven: N
tOEon
tOEoff
SLOE
t=1 t=4 T=1 T=4
Figure 10-13. Slave FIFO Synchronous Read Sequence and Timing Diagram[13]
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
FIFO POINTER
N
SLOE
N
SLRD
N+1
SLOE SLRD
N+1
SLOE
N+1
SLRD
N+2 N+2
N+3 N+3
N+4
SLRD
N+4
SLOE
N+4 Not Driven
FIFO DATA BUS Not Driven
Driven: N
N+1
Not Driven
N+1
N+4
N+4
Figure 10-14. Slave FIFO Synchronous Sequence of Events Diagram Figure 10-13 shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read. * At t = 0 the FIFO address is stable and the signal SLCS is asserted (SLCS may be tied low in some applications). Note: tSFA has a minimum of 25 ns. This means when IFCLK is running at 48 MHz, the FIFO address set-up time is more than one IFCLK cycle. * At t = 1, SLOE is asserted. SLOE is an output enable only, whose sole function is to drive the data bus. The data that is driven on the bus is the data that the internal FIFO pointer is currently pointing to. In this example it is the first data value in the FIFO. Note: the data is pre-fetched and is driven on the bus when SLOE is asserted. * At t = 2, SLRD is asserted. SLRD must meet the set-up time of tSRD (time from asserting the SLRD signal to the rising edge of the IFCLK) and maintain a minimum hold time of tRDH (time from the IFCLK edge to the deassertion of the SLRD signal). If the SLCS signal is used, it must be asserted Document #: 001-04247 Rev. *A with SLRD, or before SLRD is asserted (i.e., the SLCS and SLRD signals must both be asserted to start a valid read condition). * The FIFO pointer is updated on the rising edge of the IFCLK, while SLRD is asserted. This starts the propagation of data from the newly addressed location to the data bus. After a propagation delay of tXFD (measured from the rising edge of IFCLK) the new data value is present. N is the first data value read from the FIFO. In order to have data on the FIFO data bus, SLOE MUST also be asserted. The same sequence of events are shown for a burst read and are marked with the time indicators of T = 0 through 5. Note: For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle, on the rising edge of the clock the FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus.
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10.13.2 Single and Burst Synchronous Write
tIFCLK
IFCLK
tSFA tFAH tSFA tFAH
FIFOADR
t=0
tSWR
tWRH
T=0
>= tSWR
>= tWRH
SLWR
t=2 t=3 T=2 T=5
SLCS
tXFLG tXFLG
FLAGS
tSFD tFDH N
t=1 T=1
tSFD N+1
tFDH
tSFD N+2
tFDH
tSFD N+3
T=4
tFDH
DATA
T=3
tSPE
tPEH
PKTEND
Figure 10-15. Slave FIFO Synchronous Write Sequence and Timing Diagram[13] The Figure 10-15 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes as a short packet using the PKTEND pin. * At t = 0 the FIFO address is stable and the signal SLCS is asserted. (SLCS may be tied low in some applications.) Note: tSFA has a minimum of 25 ns. This means when IFCLK is running at 48 MHz, the FIFO address set-up time is more than one IFCLK cycle. * At t = 1, the external master/peripheral must output the data value onto the data bus with a minimum set up time of tSFD before the rising edge of IFCLK. * At t = 2, SLWR is asserted. The SLWR must meet the setup time of tSWR (time from asserting the SLWR signal to the rising edge of IFCLK) and maintain a minimum hold time of tWRH (time from the IFCLK edge to the deassertion of the SLWR signal). If SLCS signal is used, it must be asserted with SLWR or before SLWR is asserted (i.e., the SLCS and SLWR signals must both be asserted to start a valid write condition). * While the SLWR is asserted, data is written to the FIFO and on the rising edge of the IFCLK, the FIFO pointer is incremented. The FIFO flag will also be updated after a delay of tXFLG from the rising edge of the clock. The same sequence of events are also shown for a burst write and are marked with the time indicators of T = 0 through 5. Note: For the burst mode, SLWR and SLCS are left asserted for the entire duration of writing all the required data values. In this burst write mode, once the SLWR is asserted, the data on the FIFO data bus is written to the FIFO on every rising edge of IFCLK. The FIFO pointer is updated on each rising edge of IFCLK. In Figure 10-15, once the four bytes are written to the FIFO, SLWR is deasserted. The short 4-byte packet can be committed to the host by asserting the PKTEND signal. There is no specific timing requirement that needs to be met for asserting the PKTEND signal with regards to asserting the SLWR signal. PKTEND can be asserted with the last data value or thereafter. The only requirement is that the set-up time tSPE and the hold time tPEH must be met. In the scenario of Figure 10-15, the number of data values committed includes the last value written to the FIFO. In this example, both the data value and the PKTEND signal are clocked on the same rising edge of IFCLK. PKTEND can also be asserted in subsequent clock cycles. The FIFOADDR lines should be held constant during the PKTEND assertion. Although there are no specific timing requirement for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. Additional timing requirements exists when the FIFO is configured to operate in auto mode and it is desired to send two packets: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word packet committed manually using the PKTEND pin. In this case, the external master must make sure to assert the PKTEND pin at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to Figure 107 for further details on this timing.
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10.13.3 Sequence Diagram of a Single and Burst Asynchronous Read
tSFA tFAH tSFA tFAH
FIFOADR
t=0
tRDpwl
tRDpwh
T=0
tRDpwl
tRDpwh
tRDpwl
tRDpwh
tRDpwl
tRDpwh
SLRD
t=2 t=3 T=2 T=3 T=4 T=5 T=6
SLCS
tXFLG
tXFLG
FLAGS
tXFD tXFD N tOEoff tOEon N+1 tXFD N+2 tXFD N+3 tOEoff
DATA
Data (X) Driven tOEon
N
SLOE
t=1 t=4 T=1 T=7
Figure 10-16. Slave FIFO Asynchronous Read Sequence and Timing Diagram[13]
SLOE SLRD SLRD SLOE SLOE SLRD SLRD SLRD SLRD SLOE
FIFO POINTER
N
N Driven: X
N N
N+1 N
N+1 Not Driven
N+1 N
N+1 N+1
N+2 N+1
N+2 N+2
N+3 N+2
N+3 Not Driven
FIFO DATA BUS Not Driven
Figure 10-17. Slave FIFO Asynchronous Read Sequence of Events Diagram Figure 10-16 diagrams the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read. * At t = 0 the FIFO address is stable and the SLCS signal is asserted. * At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is previous data, it data that was in the FIFO from a prior read cycle. * At t = 2, SLRD is asserted. The SLRD must meet the minimum active pulse of tRDpwl and minimum de-active pulse width of tRDpwh. If SLCS is used then, SLCS must be in asserted with SLRD or before SLRD is asserted (i.e., the SLCS and SLRD signals must both be asserted to start a valid read condition). * The data that will be driven, after asserting SLRD, is the updated data from the FIFO. This data is valid after a propagation delay of tXFD from the activating edge of SLRD. In Figure 10-16, data N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle (i.e.,SLRD is asserted), SLOE MUST be in an asserted state. SLRD and SLOE can also be tied together. The same sequence of events is also shown for a burst read marked with T = 0 through 5. Note: In burst read mode, during SLOE is assertion, the data bus is in a driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented.
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PRELIMINARY DRAFT CY7C68033/CY7C68034
10.13.4 Sequence Diagram of a Single and Burst Asynchronous Write
tSFA tFAH tSFA tFAH
FIFOADR
t=0
tWRpwl
tWRpwh
T=0
tWRpwl
tWRpwh
tWRpwl
tWRpwh
tWRpwl
tWRpwh
SLWR
t =1 t=3 T=1 T=3 T=4 T=6 T=7 T=9
SLCS
tXFLG
tXFLG
FLAGS
tSFD tFDH tSFD tFDH N+1
T=2 T=5
tSFD tFDH N+2
tSFD tFDH N+3
T=8
DATA
t=2
N
tPEpwl
tPEpwh
PKTEND
Figure 10-18. Slave FIFO Asynchronous Write Sequence and Timing Diagram[13] Figure 10-18 diagrams the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the 4-byte-short packet using PKTEND. * At t = 0 the FIFO address is applied, insuring that it meets the set-up time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications). * At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum de-active pulse width of tWRpwh. If the SLCS is used, it must be in asserted with SLWR or before SLWR is asserted. * At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR. * At t = 3, deasserting SLWR will cause the data to be written from the data bus to the FIFO and then increments the FIFO pointer. The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR. The same sequence of events are shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note: In the burst write mode, once SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incremented. In Figure 10-18 once the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed to the host using the PKTEND. The external device should be designed to not assert SLWR and the PKTEND signal at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion.
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PRELIMINARY DRAFT CY7C68033/CY7C68034
11.0 Ordering Information
Ordering Code Silicon for battery-powered applications CY7C68034-56LFXC Silicon for non-battery-powered applications CY7C68033-56LFXC Development Kit CY3686 EZ-USB NX2LP-Flex Development Kit 8x8 mm, 56 QFN - Lead-free 8x8 mm, 56 QFN - Lead-free Description
Table 11-1. Ordering Information
12.0
Package Diagrams
TOP VIEW
SIDE VIEW
0.08[0.003] C
BOTTOM VIEW
A
7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] N 1
1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018]
0.80[0.031] DIA.
2
E-PAD
7.70[0.303] 7.80[0.307] 7.90[0.311] 8.10[0.319]
(PAD SIZE VARY BY DEVICE TYPE)
0.30[0.012] 0.50[0.020]
0-12 0.50[0.020] 6.45[0.254] 6.55[0.258]
0.24[0.009] 0.60[0.024]
(4X)
C SEATING PLANE
Figure 12-1. 56-Lead QFN 8 x 8 mm LF56A
13.0
PCB Layout Recommendations[17]
The following recommendations should be followed to ensure reliable high-performance operation: * At least a four-layer impedance controlled boards is recommended to maintain signal quality. * Specify impedance targets (ask your board vendor what they can achieve) to meet USB specifications. * To control impedance, maintain trace widths and trace spacing. * Minimize any stubs to avoid reflected signals. * Connections between the USB connector shell and signal ground must be done near the USB connector.
* Bypass/flyback caps on VBUS, near connector, are recommended. * DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of 20-30 mm. * Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. * No vias should be placed on the DPLUS or DMINUS trace routing unless absolutely necessary. * Isolate the DPLUS and DMINUS traces from all other signal traces as much as possible.
Note: 17. Source for recommendations: EZ-USB FX2TMPCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
Document #: 001-04247 Rev. *A
6.45[0.254] 6.55[0.258]
51-85144-*D
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PRELIMINARY DRAFT CY7C68033/CY7C68034
14.0 Quad Flat Package No Leads (QFN) Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper (Cu) fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the NX2LP-Flex to the PCB through the device's metal paddle on the bottom side of the package. It is then conducted from the PCB's thermal pad to the inner ground plane by a 5 x 5 array of vias. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN's metal die paddle must be soldered to the PCB's thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process. For further information on this package design please refer to the application note Surface Mount Assembly of AMKOR's MicroLeadFrame (MLF) Technology. This application note can be downloaded from AMKOR's website from the following URL: http://www.amkor.com/products/notes_papers/ MLF_AppNote_0902.pdf. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. Figure 14-1 below displays a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that "No Clean" type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow. Figure 14-2 is a plot of the solder mask pattern and Figure 143 displays an X-Ray image of the assembly (darker areas indicate solder).
0.017" dia Solder Mask Cu Fill Cu Fill
PCB Material
0.013" dia
PCB Material
Via hole for thermally connecting the QFN to the circuit board ground plane.
This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane
Figure 14-1. Cross-section of the Area Underneath the QFN Package
Figure 14-2. Plot of the Solder Mask (White Area)
Figure 14-3. X-ray Image of the Assembly SmartMedia is a trademark of ????? EZ-USB is a registered trademark and EZ-USB NX2LP, EZ-USB NX2LP-Flex, and ReNumeration are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY DRAFT CY7C68033/CY7C68034
Document History Page
Document Title: CY7C68033/CY7C68034 EZ-USB NX2LP-FlexTM Flexible USB NAND Flash Controller Document #: 001-04247 Rev. *A REV. ** *A ECN NO. 388499 394699 Issue Date See ECN See ECN Orig. of Change GIR XUT Preliminary draft. Minor Change: Upload datasheet to external website. Publicly announcing the parts. No physical changes to document were made. Description of Change
Document #: 001-04247 Rev. *A
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